集成电路设计在寄存器传输级的设计方法已经非常成熟。
寄存器传输级（RTL）描述是目前应用最广泛的电路设计描述形式。
The Register Transfer Level (RTL) behavioral descriptions are widely used in IC designs.
还有一些人会说esl是优于寄存器传输级(rtl)的更高的抽象层次。
Still others would say that ESL refers to anything that's at a higher level of abstraction than register transfer level (RTL) representations.
此外，还用QUARTURSII软件对仿真控制逻辑进行了寄存器传输级的仿真与验证。
In addition, we verified and emulated the emulating logic by Register Transfer Language. Last of all, we presented the test program and circuit with QUARTURSII.
上述工作是为了建立一个将寄存器传输级语言描述翻译成硬件逻辑图的自动逻辑综合系统。
The above work is intended to set up an automatic logic synthesis system to translate a register transfer level language descriptions into hardware logic diagrams.
本文主要是对大规模、超大规模集成电路寄存器传输级（RTL）的自动测试产生算法进行研究。
This dissertation focuses on automatic test generation (ATPG) algorithms for very large-scale integrated circuits at register-transfer-level (RTL).
高层次综合也叫行为级综合，其基本任务是完成数字系统行为描述到寄存器传输级（RTL）描述的转换。
The main task is translating the behavioral description of a digital system into the design of RTL(Register Transfer Level).
验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。
Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level (RTL) is a promising solution.
寄存器传输级(rtl)综合实现从rtl行为描述到门级结构描述的转换，是目前EDA设计行业的主流设计方法。
As the behavior of digital system can be fully described by the register transfer level (RTL) behavior descriptor, so RTL synthesis has become the mainstream design method in EDA domain.
文章讨论了寄存器传输级结构对综合方法的影响，并提出使用分模块的寄存器传输级结构作为高层次综合的目标结构。
The influence of architectures on synthesis methods is discussed, and a clustered register transfer level architecture as object architecture is presented.
由于寄存器传输级(rtl)行为描述可以精确地确定数字系统的操作，所以寄存器传输级综合成为当前EDA行业的主流设计方法。
Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain.
由于寄存器传输级(rtl)行为描述可以精确地确定数字系统的操作，所以寄存器传输级综合成为当前EDA行业的主流设计方法。
Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain.
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