分别采用三种不同的技术对多芯片组件互连延迟进行建模，并给出了相应的解。
Interconnection delay in MCM 's is modeled by using three different techniques, and the associated formulas are also derived.
在前期设计阶段考虑互连延迟问题已是当前研究的重要课题。建立以互连为中心的综合方法是当前的一个棘手问题，尚未有成熟的方法。
Considering interconnect delay in early design stages is a hot spot and how to establish an interconnect-centered synthesis method is a hard task, yet without mature approaches.
深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
比起其他超级计算机中所使用的无限带宽（Infiniband）连接技术，这种新型的互连方式明显拥有更高的带宽和更低的延迟时间。
This interconnect has significantly higher bandwidth and lower latency than previous interconnects, such as the Infiniband interconnect that is standard on many other supercomputers.
在FPGA的情况下，所使用的元胞块数量也会在很大程度上影响布线后的最终延迟，因为大多数延迟是由存在的可编程互连所引起的布线延迟。
In the case of FPGAs, the number of blocks used will also greatly influence the final delay after routing because most of the delays is the wiring delays due to the programmable interconnect existed.
本文讨论了影响互连线延迟的因素，并讨论了从降低信号摆幅、改变开关阈值方面解决延迟、功耗等问题。
The factors that affect the interconnect wire delay and the resolution ways from to lower the signal swing and change switch threshold value aspect are described in this paper.
本论文着重论述未来CMOS进入纳米尺寸的关键挑战，如：电源电压和阈值电压减小、短沟效应、量子效应、杂质数起伏以及互连线延迟等影响。
Key challenges on CMOS scaling down into nanometer regime are discussed, such as power supply and threshold voltage, short-channel effect, quantum effect, random doping distribution and wire delay.
本文重点研究高性能计算机“高带宽、低延迟”互连系统技术，以支持高性能计算机系统计算能力和效率的更好发挥。
Some problems in realizing the "high bandwidth, low latency" of interconnection system are solved to increase the interconnection communication ability and efficiency.
我们再也不能如同处理低速设计一般，视互连为集总电容或简单的延迟线。
It is no longer possible to model interconnects as lumped capacitors or simple delay lines, as could be done on slower designs.
并行处理器互连网络的路由算法异常复杂，电路延迟长，逻辑规模巨大，是制约高性能并行处理器提高频率、降低功耗的瓶颈。
The router arithmetic of the parallel processor is complex. The circuit has long latency and the logic has the huge size.
并行处理器互连网络的路由算法异常复杂，电路延迟长，逻辑规模巨大，是制约高性能并行处理器提高频率、降低功耗的瓶颈。
The router arithmetic of the parallel processor is complex. The circuit has long latency and the logic has the huge size.
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