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分别采用三种不同的技术对多芯片组件互连延迟进行建模，并给出了相应的解。
Interconnection delay in MCM 's is modeled by using three different techniques, and the associated formulas are also derived.
在前期设计阶段考虑互连延迟问题已是当前研究的重要课题。建立以互连为中心的综合方法是当前的一个棘手问题，尚未有成熟的方法。
Considering interconnect delay in early design stages is a hot spot and how to establish an interconnect-centered synthesis method is a hard task, yet without mature approaches.
深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
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