这让处理器可以提前准备分支操作（例如预取指令）。
This allows the processor to prepare for the branch ahead of time (prefetching the instructions, for instance).
在获取每条指令期间会出现某种延迟，可以通过预取指令并对其进行存储以用于后续的执行，从而避免延迟。
Fetching each instruction involves a certain latency that can be avoided by prefetching instructions and storing them for later execution.
流水线是 CPU所使用的一个众所周知的概念，它用于减少取指令-译码-执行 周期中出现的延迟。
Pipelining is a well-known concept employed by CPUs for reducing the latency involved in the fetch-decode-execute cycle.
它从存储器中取指令，提供存储器需要的地址和控制信号。
It fetches instructions from memory, supplying the address and control signals needed by memory to access its data.
每个被映射的页面都有读、写以及取指令(也叫执行)的限制。
Each mapped page is restricted in the types of operations that may be performed on its contents: read, write, and instruction fetch (also called execute).
取指令对于每个指令来说都是个普通操作，它包括从内存单元中读指令。
The instruction fetch is a common operation for each instruction , and consists of reading an instruction from a location in memory.
该预取指令可以与系统互连事务一起或作为单独的事务发送到系统中包括所述目标处理器的设备。
The prefetch directive may be sent along with system interconnection transactions or sent as a separate transaction to devices including the target processor in the system.
在单指令流单数据流结构中，有单一的指令周期，在执行前，单个处理机按序取操作数。
In an SISD architecture there is a single instruction cycle; operands are fetched serially into a single processing unit before execution.
无论何时从内存中取一个指令，指令指针都会经指令tlb的翻译后指向物理地址。
Whenever an instruction is fetched from memory, the instruction pointer is translated via the instruction TLB into a physical address.
无论何时从内存中取一个指令，指令指针都会经指令tlb的翻译后指向物理地址。
Whenever an instruction is fetched from memory, the instruction pointer is translated via the instruction TLB into a physical address.
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