这让处理器可以提前准备分支操作(例如预取指令)。
This allows the processor to prepare for the branch ahead of time (prefetching the instructions, for instance).
在获取每条指令期间会出现某种延迟,可以通过预取指令并对其进行存储以用于后续的执行,从而避免延迟。
Fetching each instruction involves a certain latency that can be avoided by prefetching instructions and storing them for later execution.
流水线 是 CPU 所使用的一个众所周知的概念,它用于减少取指令-译码-执行 周期中出现的延迟。
Pipelining is a well-known concept employed by CPUs for reducing the latency involved in the fetch-decode-execute cycle.
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