For intra prediction, the boundary pixels are reshuffled before feeding into the systolic array.
对于内部预测，我们先将边界点重组后在丢入过滤器中。
The realization of mapping a class of nested loop algorithms to linear systolic array is studied.
研究了一类多重循环算法的线性脉动阵列实现。
A novel systolic array architccture for computing discrete orthogonal transforms such as DCT, DHT(DWT) and DFT is proposed.
本文提出一种新型计算离散正交变换如DCT、DHT（DWT）和DFT的脉动阵列实现。
It adopts a new systolic array architecture, which can improve the speed by increasing the frequency without the size increased.
设计采用的新型心动阵列结构，可以在有效控制芯片面积的前提下，极大地提高运算频率，从而提高运算速度。
Implementing large scale of systolic array in FPGA to accelerate pare-wise alignment can improve the efficiency of alignment remarkably.
在FPGA上实现大规模脉动式阵列对双序列比对算法进行加速能够大幅度提高比对的效率。
To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。
This structure divides wavefront control calculation into recursive algorithm and convolution algorithm, and maps them to respectively systolic array by using canonical mapping method.
该结构将波前控制算法分为递归运算和卷积运算两部分后，采用规范映射方法将其分别映射到脉动阵列，再将两个阵列链接以实现单路的波前控制运算。
In this paper, we preset the processing elements based on a special butterfly computation and discrible the systolic array implementations for computing DCT, DHT(DWT) and DFT respectively.
文中绐出了两种基于特殊蝶形运算的处理单元和两种计算DCT，DHT（DWT）和DFT的脉动阵列实现。
This article provides a general analysis and discus sion of the algorithms, structure, application perspectives of VLSI array proces sots, including Systolic and Wavefront.
本文将分析并讨论脉动与波前阵列处理器的算法、结构和应用。
This article provides a general analysis and discus sion of the algorithms, structure, application perspectives of VLSI array proces sots, including Systolic and Wavefront.
本文将分析并讨论脉动与波前阵列处理器的算法、结构和应用。
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