The reliability of strain silicon, gate dielectric and copper interconnection are discussed, and some new researches are presented.
简介了应变硅材料、栅介质的工艺及铜互连的可靠性，并对新的研究方向做了介绍。
It will also use copper interconnects, low-k, strain silicon and other features. Like 32-nm, Intel will make use of 193-nm immersion lithography.
这款产品将使用Intel第三代HKMG工艺，第五代硅应变技术，另外与32nm类似，22nm制程仍将继续使用193nm液浸式光刻技术。
Strained silicon is a fundamental component of all recent microprocessors. The reason for its success is that local strain-induced deformation in the crystal lattice improves processor performance.
“变形”硅是所有最新的处理器的基本组成部分，原因是：晶格里应变诱发的形变提升了处理器的性能。
The new siloxane linkage can experience strain if the two silicon atoms are not sufficiently close enough for the formation of a normal siloxane linkage.
如果这两个硅原子之间的距离大于形成正常硅氧烷键所需的距离，新形成的硅氧烷键就会存在张力。
If the strain exceeds the tolerable limit, the Si-O-Si linkage can break easily at high temperature and lead to the creation of positive and negative charges on silicon and oxygen atoms, respectively.
如果张力超过耐受极限，硅氧烷键就很易在高温下发生断裂并在硅和氧原子上分别形成正负电荷。
The maximum cumulative equivalent creep strain was located in inner solder ball and at the edge of silicon chip.
最大累积等效蠕变应变位于内层焊点，且在芯片边缘。
The maximum cumulative equivalent creep strain was located in inner solder ball and at the edge of silicon chip.
最大累积等效蠕变应变位于内层焊点，且在芯片边缘。
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