An optimal sequencing of the storage elements in the single scan chain design for - testability is presented in the paper.
本文提出了扫描设计中存储元件在扫描链中的最优排序方法。
This paper chooses USB logic analyzer as a typical tested object, and carries through a second develop to design it supporting IEEE 1149.1 boundary-scan function for testability.
本文以usb逻辑分析仪作为一种典型的被测对象，进行了可测性设计的再开发工作，使其具有支持IEEE 1149.1边界扫描功能的设备结构。
There are some common methods of design for testability, such as boundary scan test and so on.
目前常见的可测试性设计方法主要有改善设计法、结构设计法和边界扫描测试法等几种。
A partial scan algorithm for BIST, which combines the structure analysis and testability analysis, is presented in this paper.
提出了一种在内建自测试(BIST)中进行部分扫描的算法，此算法综合了电路的结构分析和可测性分析。
As a standard technique of test and Design-For-Testability for testing the digital printed circuit board, Boundary-Scan technique has obtained widespread application in electronic equipment.
边界扫描技术是一种标准的数字电路测试及可测试性设计方法，它在工业界得到了广泛的应用。
As a standard technique of test and Design-For-Testability for testing the digital printed circuit board, Boundary-Scan technique has obtained widespread application in electronic equipment.
边界扫描技术是一种标准的数字电路测试及可测试性设计方法，它在工业界得到了广泛的应用。
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