non scan design for testability 非扫描可测性设计
non-scan design for testability 非扫描可测性设计
non-scan des ign for testability 非扫描可测性设计
An optimal sequencing of the storage elements in the single scan chain design for - testability is presented in the paper.
本文提出了扫描设计中存储元件在扫描链中的最优排序方法。
This paper chooses USB logic analyzer as a typical tested object, and carries through a second develop to design it supporting IEEE 1149.1 boundary-scan function for testability.
本文以usb逻辑分析仪作为一种典型的被测对象，进行了可测性设计的再开发工作，使其具有支持IEEE 1149.1边界扫描功能的设备结构。
There are some common methods of design for testability, such as boundary scan test and so on.
目前常见的可测试性设计方法主要有改善设计法、结构设计法和边界扫描测试法等几种。
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