Methods and computer readable media for performing scan-based testing of circuits using one or more test clock control structures are disclosed.
公开了使用一个或多个测试时钟控制结构的来执行基于扫描测试的方法和计算机可读介质。
Fault injection emulation platform based on Joint Test Action Group (JTAG) boundary scan and dynamic partial reconfiguration is proposed.
提出基于JTAG边界扫描技术和动态局部重配置的错误注入模拟平台。
We have developed a new On-line Connecting Test System based on JTAG boundary scan for computer plug-unit or system.
在某计算机系统中设计了基于JTAG边界扫描计算机插件或系统在线导通测试系统，这是一个新颖通用的系统。
On the basis of research on the bound ary-scan architecture and TAP controller, the paper implements a design for a t ap interface based on JTAG specification in a test system.
该文在研究边界扫描体系结构和TAP接口控制器的基础上，在一个测试系统中，实现了基于JTAG规范的主ta P接口设计。
Based on the research of primary DFT method and the structure characteristic of designed CPU, the article combines the boundary scan and Build-In Self-Test based on BILBO to test.
本文在对目前主要的可测性设计方法进行研究的基础上，根据所设计CPU的结构特点，采用了边界扫描技术和基于BILBO的内建自测试技术结合的可测性设计方案。
A scan test scheme based on scan chain disabling technique has been proposed, which can effectively reduce test power. However, its test application time is long.
一种基于扫描链阻塞技术的扫描测试结构被提出来，该结构有效地降低了测试功耗，但其测试应用时间较长。
The invention discloses a memorizer test device based on a scan chain and a use method thereof.
本发明公开了一种基于扫描链的存储器测试装置及其使用方法。
For the test application time can be reduced effectively, this paper proposes an approach based on scan chain disabling technique, in view of incompatible test vector compression method.
为进一步降低测试功耗及测试应用时间，提出一种基于扫描链阻塞技术且针对非相容测试向量的压缩方法。
Meanwhile the testing of SOC become more difficult and complex, Boundary-Scan-based Built-in-Test technology give a new solution.
与此同时，片上系统的测试问题也随之产生，基于边界扫描的内建自测试技术为片上系统的测试提供了新的解决方案。
Meanwhile the testing of SOC become more difficult and complex, Boundary-Scan-based Built-in-Test technology give a new solution.
与此同时，片上系统的测试问题也随之产生，基于边界扫描的内建自测试技术为片上系统的测试提供了新的解决方案。
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