FIG. 5 illustrates an example of pulse width generator 404, according to another embodiment of the present invention.
图5示出依照本发明另一个实施例的脉冲宽度发生器404的示例。
Thus, pulse width generator 404 generates a delay between a falling edge of VIN and a subsequent falling edge of VOUT.
因此，脉冲宽度发生器404在VIN下降沿和随后的VOUT下降沿之间产生延迟。
According to further embodiments of the present invention, pulse width generator 404 can have 3, 4, 5, 6, or more separate delay paths.
依照本发明进一步的实施例，脉冲宽度发生器404可具有3,4,5,6或更多个分离的延迟路径。
FIG. 5 illustrates an example of a pulse width generator with two alternate delay paths, according to another embodiment of the present invention.
图5图示说明依照本发明的另一实施例具有两个交替延迟路径的脉冲宽度发生器的示例。
FIG. 6a illustrates an example of a pulse width generator that includes a temperature sensitive diode, according to a further embodiment of the present invention.
图6a图示说明依照本发明进一步的实施例包括温度敏感二极管的脉冲宽度发生器的示例。
Pulse width generator 404 can include, for example, one or more delay circuits.
脉冲宽度发生器404可包括例如一个或更多个延迟电路。
Pulse width generator 404 generates a falling edge in VOUT a delayed period of time after the falling edge in VIN.
在VIN下降沿后的延迟时间周期中，脉冲宽度发生器404产生VOUT的下降沿。
Pulse width generator 404 generates a falling edge in VOUT a delayed period of time after the falling edge in VIN.
在VIN下降沿后的延迟时间周期中，脉冲宽度发生器404产生VOUT的下降沿。
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