Listing 5. lsattr output illustrating processor architecture.
清单5. lsattr输出说明了处理器的体系结构。
This is native code, compiled to the processor architecture in use.
这是原生代码，在使用时由处理器构架编译。
Basis processor became the architecture SPI stream processor architecture.
处理器的基础上，成为建筑的SPI流的处理器架构。
Processor architecture makes a lot less difference when compiling code than APIs do.
和API相比，处理器体系架构在编译代码时不会造成那么多的区别。
The source and destination servers must be at least POWER6 processor architecture-based systems.
源服务器和目标服务器必须至少位于基于POWER 6处理器架构的系统中。
The command takes three options: the operating system name, the processor architecture, and the profile.
此命令接受三个选项：操作系统名、处理器架构和概要文件。
A design method for control network nodes based on CPLD and multi-processor architecture is proposed in this paper.
论文提出了一种基于CPLD和多处理器结构的控制网络节点设计方法。
Thankfully, the three steps listed previously don't require inventing any truly new processor architecture concepts.
值得庆幸的是，前面所列的这三个步骤不需要发明任何真正新的处理器架构概念。
This paper presents VISA, a scalable processor architecture based on dynamic binary translation (BT) and optimization.
本文提出一种基于动态二进制翻译优化的可扩展处理器结构VISA。
The old publisher policy assembly cannot service your assembly once your assembly has a different processor architecture.
如果程序集具有不同的处理器结构，旧的发行者策略程序集则无法处理该程序集。
The thesis presents a highly efficient processor architecture design methodology for local compute-intensive applications.
本文提出了一种针对局部计算密集型应用的一种高效处理器架构的设计方法。
This support comes after Microsoft officially made available a copy of 64-bit Windows that supports this processor architecture.
该支持是在Microsoft正式使得支持该处理器架构的 64位Windows副本可用之后实现的。
To obtain safe and tight WCET estimation, it is necessary to take account of the features of a target processor architecture.
为获得安全而紧致的WCET估计，需要考虑执行程序的目标处理器的体系结构特征。
The LEON processor architecture provides designers with a flexible a design environment for customization to individual requirements.
LEON处理器为设计人员提供了一个灵活的设计环境，可以定制单独的需求。
Unlike other languages, assembly programming involves understanding the processor architecture of the machine that is being programmed.
与其他语言不同，汇编语言要求开发人员了解编程所用机器的处理器体系结构。
Early microprocessor speed and functionality while still not high enough, but can be adopted to solve the multi-processor architecture.
早期的微处理器速度和功能虽还不够高，但可以通过多处理器结构来解决。
The POWER5 + processor architecture (running the AIX 5l operating system) addresses the page table problem by introducing multiple page sizes.
POWER5 +处理器架构(运行AIX 5l操作系统)通过引入多页面大小来解决页表问题。
This thesis aims to solve the problem that the network processor architecture faces and research the method of designing network processor.
本文针对网络处理器体系结构面临的问题，研究网络处理器的设计方法。
First, trim the processor architecture of any features and functions that do not directly provide a performance boost to the target algorithm.
首先，除去那些不直接提供目标算法性能提升的所有特性和功能的处理器架构。
The research and experimental results in this dissertation can provide direction for the design and optimization of tiled processor architecture.
本文的研究工作和结果可用于指导分片式处理器的体系结构设计和进一步的优化。
In fact, this is one of the reasons why most of the general-purpose processor architecture companies are moving to multi-core solutions themselves.
事实上，这也是为什么大多数通用处理器架构的公司正在向多核心解决方案转型的原因之一。
The processor's fault tolerant mechanism mainly using temporal redundancy technique was implemented by modifying superscalar processor architecture.
处理器的容错机制是通过修改超标量体系结构，利用时间冗余技术实现的。
It is a 10-inch screen attached to a cheaper ARM processor architecture, smaller battery, a few sensors (like GPS, accelerometers, camera) and a touch screen.
它只是一个10寸的显示屏加触摸屏，连接到一个成本更低的ARM处理器架构上，此外还有一些传感器(如gps、感应器、摄像头等)，和比上网本小一号的电池。
The other main type of processor architecture, CISC (the x86 processor being a popular CISC instruction set), allows for memory access in nearly every instruction.
另外一种主要的处理器体系结构CISC (x86处理器就是一种流行的CISC指令集)几乎允许在每条指令中进行内存访问。
If you don't have a compiler that can produce code to take advantage of the underlying processor architecture and instruction set, then the fastest machines will be useless.
如果您没有可以生成代码来利用底层处理器架构和指令集的编译器，那么最快的机器也将是无用的。
Modular parallel multi-processor architecture is used in this scheme, and de-multiplex and re-multiplex of relatively complicated MPEG-2transport stream can be realized.
该方案采用模块化并行多处理器结构，可实现较为复杂的MPEG-2传输流解复用、再复用的过程。
NOTE: if you develop a plug-in specific to an operating system or processor architecture, you could enter this information in the provided fields under Supported Environments.
注意：如果开发了一个特定于操作系统或处理器架构的插件，那么可以在Supported Environments下面所提供的字段中输入这些信息。
You also need to know whether the JVM correctly determines host processor architecture so that the JIT compiler can produce the correct set of instructions for that architecture.
您还需要知道J VM能否确定主机处理器的体系结构，以使得JIT编译器可以为那个体系结构生成正确的指令集。
If your host and guest operating system are targeted to the same processor architecture, then you can speed things up to near native performance using the QEMU accelerator (KQEMU).
如果主机操作系统和来宾操作系统运行于相同的处理器架构之上，那么您可以使用QEMU加速器(KQEMU)实现近似本地的性能。
If your host and guest operating system are targeted to the same processor architecture, then you can speed things up to near native performance using the QEMU accelerator (KQEMU).
如果主机操作系统和来宾操作系统运行于相同的处理器架构之上，那么您可以使用QEMU加速器(KQEMU)实现近似本地的性能。
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