A logic operation is performed on the plurality of circuit layouts to extract the patterned feature.
在该若干个电路布置上执行一逻辑操作，以撷取图案化特征结构。
A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided.
一种在半导体与罩幕制造中改善晶圆上的图案化特征结构的临界尺寸均匀性的方法。
A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided.
一种在半导体与罩幕制造中改善晶圆上的图案化特征结构的临界尺寸均匀性的方法。
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