Each pod has its own processors and memory, and is connected to the larger system through a cache-coherent interconnect bus.
每个pod具有自己的处理器和内存，并通过一条高速缓存一致性互连总线(cache - coherent interconnect bus)连接到较大的系统。
However, here we can define the Service Integration BUS (simply BUS later) as a logical cloud, that provides the mechanisms to interconnect a consumers with a providers. This logical cloud contains.
然而，我们可以定义服务集成总线(后面简称为总线)为一个逻辑云，其可以提供消费者与提供商互连的机制。
The bus structure of the system: which devices connect to which bus and which buses are interconnected (for instance, a USB - PCI interconnect)?
系统的总线结构：哪个设备连接在哪个总线上，以及哪些总线互连(例如，USB和PCI总线的互连)？
This paper introduces the problems of Signal Integrity in high-speed parallel bus interconnect design and the new design methodology.
本文介绍了高速并行总线互连设计中出现的信号完整性问题及新的设计方法学。
As the field bus, CAN is an open interconnect network, which supports multiple-group, real-time and distributed control on series connection communication.
现场总线的CAN，是一种开放式互联网络，支持多组实时、分布式控制串行通讯。
In this paper, an optical interconnection data link for PCI bus parallel interconnect has been designed and implemented using semiconductor laser diodes and PIN photo detectors.
本文采用半导体激光器和PIN光电探测器，设计和实现了用于计算机PCI总线并行互连的光互连链路。
In order to realize Ethernet and CAN bus's data conversion, Constructed a interconnect system based on embedded technology between CAN bus and Ethernet.
为了实现以太网与CAN总线的数据交换，构建了一个基于嵌入式的CAN总线与以太网互连系统。
In order to realize Ethernet and CAN bus's data conversion, Constructed a interconnect system based on embedded technology between CAN bus and Ethernet.
为了实现以太网与CAN总线的数据交换，构建了一个基于嵌入式的CAN总线与以太网互连系统。
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