Circuitry of interlaced encoder and decoder and some experimental results are then given.
介绍了我们研制的交错码的编译码器电路及实验结果。
In this paper, rs (204,188) encoder and decoder is designed, which can correct 8 errors to the maximum.
本论文设计的是RS(204,188)码的编码器和译码器，最多能纠正8个错误。
An FPGA implementation method of this scheme is presented, including BCH encoder and decoder and the interleaver.
并详细介绍了用FPGA实现该编码方案的方法，包括BCH码的编译码和交织编码。
Later this paper implements the software of modified video encoder and decoder of MPEG-4 using VC on PC platform, which verifies feasibility of modified algorithms.
随后，本文在PC机上采用VC编写了改进后的MPEG - 4视频编码器和解码器的软件，验证了对算法改进的可行性。
The image encoder and decoder based on the general high performance DSP chip has especial advantages of high reliability, small-size, fast data processing, low power consumption and flexibility.
本文所开发的基于通用高性能DSP芯片的图像编解码系统具有可靠性高、速度快、体积小、功耗低和环境适应性强等优点。
It USES the PCI interface chip SAA7146A special for media processing produced by Philips, and connects simply with video encoder, video decoder, audio encoder and decoder.
设计选用PCI多媒体接口芯片SAA7146A，方便的实现了与视频编码器、视频解码器和音频编解码器的连接。
It USES the PCI interface chip SAA7146A special for media processing produced by Philips, and connects simply with video encoder, video decoder, audio encoder and decoder.
设计选用PCI多媒体接口芯片SAA7146A，方便的实现了与视频编码器、视频解码器和音频编解码器的连接。
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