Circuitry of interlaced encoder and decoder and some experimental results are then given.
介绍了我们研制的交错码的编译码器电路及实验结果。
In this paper, rs (204,188) encoder and decoder is designed, which can correct 8 errors to the maximum.
本论文设计的是RS(204,188)码的编码器和译码器，最多能纠正8个错误。
An FPGA implementation method of this scheme is presented, including BCH encoder and decoder and the interleaver.
并详细介绍了用FPGA实现该编码方案的方法，包括BCH码的编译码和交织编码。
There are both two DSPs to accomplish the encoding and decoding with pipeline technique in the encoder and decoder.
采用流水线的工作方式，在编码和解码端均有两片DSP并行来完成编码和解码。
The design of two-dimensional optical orthogonal codes encoder and decoder in optical code-division multiple access system;
提出一种适用于光正交码作为地址码的光码分多址多用户干扰并行干扰抑制系统。
Nonlinear encoder and decoder are common techniques of digital signal processing that are widely used in digital communications.
非线性编码与解码是现代数字通信对数字信号处理常用的一种技术。
Later this paper implements the software of modified video encoder and decoder of MPEG-4 using VC on PC platform, which verifies feasibility of modified algorithms.
随后，本文在PC机上采用VC编写了改进后的MPEG - 4视频编码器和解码器的软件，验证了对算法改进的可行性。
It USES the PCI interface chip SAA7146A special for media processing produced by Philips, and connects simply with video encoder, video decoder, audio encoder and decoder.
设计选用PCI多媒体接口芯片SAA7146A，方便的实现了与视频编码器、视频解码器和音频编解码器的连接。
Key aspects of well-logging cable data transmission system, such as cable transmission features, modulation technology, design of Manchester encoder and decoder based on complica.
介绍了影响应答器数据传输电缆特性阻抗的主要因素，并结合生产实践讨论了如何进行质量控制。
Motion estimation and compensation costs the most resource in MPEG-4 encoder and decoder, and people are always seeking the emulative algorithm of motion estimation and compensation.
运动估计和补偿在MPEG - 4编码器和解码器中占用资源最多，人们直寻求较有竞争力的运动估计和补偿的算法。
Based on a thorough study of Soft-IP design methodologies, two sort of widely-used Manchester encoder and decoder Soft-IP cores have been designed, in need of developing subsequence instruments.
在深入研究可复用IP软核设计方法的基础上，结合开发团队实际需要，设计了常用的两款曼彻斯特编译码器IP软核。
The image encoder and decoder based on the general high performance DSP chip has especial advantages of high reliability, small-size, fast data processing, low power consumption and flexibility.
本文所开发的基于通用高性能DSP芯片的图像编解码系统具有可靠性高、速度快、体积小、功耗低和环境适应性强等优点。
To compress data, the LZ77 algorithm replaces portions of the data with references to matching data that has already passed through both the encoder and the decoder.
为了压缩数据，LZ 77算法使用对匹配数据的引用来取代数据部分。匹配数据已经通过编码器和解码器传递。
This rule can be inverted to store a 0 if the run begins with a 0 bit, but the effect is the same as long as both the encoder and the decoder of the inversion list agree on this detail.
如果开始出现的是0 ，那么这个规则需要改变，但效果是一样的，因为编码器和解码器都遵循这一规则。
By using the multiple ion implantation technique, novel CMOS quaternary decoder and encoder are designed.
利用多级离子注入技术，一种新型的CMOS四值译码器与编码器被设计。
With a 16-bit internal hardware counter, the decoder is feasible for interfacing encoder and CPU in the development of multi-axis closed-loop movement control system.
解码器内部具有16位硬件计数器，与CPU接口方便，非常适合于多轴闭环运动控制系统的开发。
The decoder is essentially an inverse of the structure and methods of the encoder, and results in a reproduced audio signal that cannot be audibly distinguished from the original signal.
解码器实质上是编码器的逆向结构和方法，产生一个听觉上不能与原始信号区分开的被还原的音频信号。
In addition, 8b10b encoder and 10b8b decoder are designed on base of FPGA for meet with the need for the type of transmission data in fiber communication system.
另外针对光纤通信系统对传输信号码型的要求，利用FPGA设计了8b10 B编码器和10b8 B译码器。
The paper proposes a new method for Hanming encoder and Hanming decoder which is based on the VHDL language.
文章提出了一种新的基于VHDL语言的汉明码的编码和译码的实现方法。
The encoder of length 16200 and rate 2/3 IRA codes is designed and implemented with FPGA, and the corresponding decoder structure is designed.
用FPGA设计并实现了标准中码长16200，码率2/3IRA码的编码器，且设计出相应的译码器结构。
Encoders from 8-3 priority encoder for example, and decoder includes 3-8 decoder and the 2-4 examples of the two decoder modules.
编码器由8线- 3线优先编码器作为实例代表，译码器则包含3线- 8线译码器和2线- 4线译码器两个实例模块组成。
This paper introduces wireless transmitter and receiver circuit based on encoder chip PT2262 and decoder chip PT22720, and presents some typical applications in medical instrument development.
介绍了基于编码芯片PT 2262和解码芯片PT 2272的无线发射及接收电路，介绍了由它们构成的无线传送技术在医学仪器设计中的典型应用。
The network of intersections between input and output leads in a computer, functioning as an encoder or a decoder.
模型，压模计算机中输入和输出之间的交叉网，用作编码。
The FPGA is designed as a MVB controller which consists of Manchester encoder, Manchester decoder, buffer, center control unit, internal memory, MCU interface and so on.
FPGA实现MV B控制器功能，分为曼彻斯特编码器、解码器、缓冲区、中央控制单元、内部存储器和单片机接口等几部分。
The encoder assembly (1) is respectively connected with a change-over switch (2), a combining beam switching control (3), the decoder assemblies (4) and (14), a storage battery (13) and the ground.
所述编码器组件（1）分别接向转向开关（2）、组合变光开关（3）、译码器组件（4）和（14）、蓄电池组（13）和地。
The encoder assembly (1) is respectively connected with a change-over switch (2), a combining beam switching control (3), the decoder assemblies (4) and (14), a storage battery (13) and the ground.
所述编码器组件（1）分别接向转向开关（2）、组合变光开关（3）、译码器组件（4）和（14）、蓄电池组（13）和地。
应用推荐