The encoder and decoder used in ATM switcher are designed using specific error correcting 1C.4.
设计了ATM交换机中编译码器模块。
参考来源 - RS码的研究与应用Combined with characteristics of underwater image, design and implementation of JPEG encoder and decoder in Quartuss II software using VerilogHDL language is produced in this article.
本文结合水声图像特点,应用VerilogHDL语言在QuartusⅡ软件环境下设计实现了JPEG基本模式编解码器。
参考来源 - JPEG编解码的FPGA仿真研究·2,447,543篇论文数据,部分数据来源于NoteExpress
Circuitry of interlaced encoder and decoder and some experimental results are then given.
介绍了我们研制的交错码的编译码器电路及实验结果。
An FPGA implementation method of this scheme is presented, including BCH encoder and decoder and the interleaver.
并详细介绍了用FPGA实现该编码方案的方法,包括BCH码的编译码和交织编码。
There are both two DSPs to accomplish the encoding and decoding with pipeline technique in the encoder and decoder.
采用流水线的工作方式,在编码和解码端均有两片DSP并行来完成编码和解码。
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