The design of chip test controller of a security chip and design for test of corresponding cores are discussed in detail.
从可测性设计角度讨论了信息安全处理芯片的芯片级测试控制器的设计以及相应核的可测性设计。
With the optimal assignment and balance design for test wrappers, four types of incremental Sequence Pair generation methods are constructed as a cyclic iteration process.
在对测试环采取最优分配和平衡优化的基础上，构造包含四种序列对递增生成方法的循环迭代过程。
Design for test is an important process in the chip design nowadays, testability design of wireless chip needs a much higher requirement of test technology.
可测试性设计是现代芯片设计中的关键环节，针对无线接入芯片的可测试性设计对测试技术有更高的要求。
For the test and verification of soft-IP, the paper presents a solution of Design For test technique, of which the BIST (Built-in Self test) is described in particular.
针对IP软核的测试、验证提出了面向测试、验证的IP软核设计方法—BIST内建自测试方法。
For the test and verification of soft-IP, the paper presents a solution of Design For test technique, of which the BIST (Built-in Self test) is described in particular.
针对IP软核的测试、验证提出了面向测试、验证的IP软核设计方法—BIST内建自测试方法。
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