Asynchronous Clock Designs ; Clifford E. Cummings.
非常精典的异步时钟域设计文章。
The adaptive filter (15) and subtractor (16) are coupled to an asynchronous clock (18) for operating at an asynchronous sample rate.
把所述自适应滤波器（15）和减法器（16）与异步时钟（18）耦合以便以异步采样率操作。
Most of the ASIC" s ever designed are driven by multiple asynchronous clocks. An important problem in multi-clock do-main design is how to avoid metastability."
绝大部分ASIC设计工程师在实际工作中都会遇到多时钟域设计的问题，多时钟域设计的一个难题是如何避免亚稳态的产生。
In design of pulsed asynchronous sequential circuits, it will solve for equations of clock and equations of state, on a symbolic Karnaugh map.
在异步时序电路设计中，它将时钟方程和状态方程的求解归在统一的符号卡诺图上进行。
Asynchronous interrupts are generated by other hardware devices at arbitrary times with respect to the CPU clock signals.
异步中断是由其他硬件设备产生的，可以在CPU时钟信号的任意时刻到来。
According to different sensitive transitions of flip-flops used in sequential circuits, design and analysis methods for asynchronous sequential circuits are proposed by using the combinatorial clock.
本文根据电路中采用的触发器的不同敏感沿，提出采用组合时钟的异步时序电路的设计和分析方法。
The parallel loading of the flip-flop can be synchronous (i. e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.
触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟)，这取决于移位寄存器的设计。
This paper introduces the process of logic design of digital circuits, and mainly explains the function of asynchronous counter and decoder. The digital clock is an example of this application.
本文介绍了数字电路系统的逻辑设计过程，并且着重阐明异步计数器和译码器的功能，数字钟是这方面应用的一个实例。
Asynchronous FIFO is a general way to communicate between different clock domains.
异步fifo是一种不同时钟域之间传递数据的常用方法。
The design of asynchronous circuits is widely used in modern VLSI design, which is able to resolve the problems of power dissipation, system speed, clock skew, etc.
异步电路的设计能够解决功耗、系统速度、时钟偏移等问题，成为当前VLSI研究的热点。
Because the short time interval which is asynchronous between the time interval measured and the clock pluses filled exists in the any time measurement.
因为对任意的时间测量都存在着被测时间间隔与填充脉冲之间所不同步的短时间间隔。
Using the clock synchronization, synchronous sampling could be realized on an asynchronous control network.
为了能在异步控制网络上实现采样同步，可采用时钟同步方法。
Using the clock synchronization, synchronous sampling could be realized on an asynchronous control network.
为了能在异步控制网络上实现采样同步，可采用时钟同步方法。
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