asynchronous clock domain 异步时钟域
asynchronous clock domains 异步时钟域
multi-asynchronous clock design 多时钟域设计
asynchronous multi-clock system 异步多时钟系统
Above all, this dissertation researched on the synchronizer design of system in asynchronous clock domain from the theory, discussed the solution for some common problem as metastabiliy, race and hazard, empty/full flag generating and etc.
综上所述,本文对异步时钟域的数据同步进行了较深入的研究,讨论了亚稳态,地址毛刺,空/满标志产生等常见问题的解决方案,并以之为理论基础成功实现了项目的设计指标。
参考来源 - 异步多时钟域系统的同步设计研究·2,447,543篇论文数据，部分数据来源于NoteExpress
应用推荐