Those traditional test generation algorithms are not applicable any more.
那些传统的测试生成算法已不再适用。
The test generation efficiency is higher comparing with other algorithms.
与其他算法相比，测试生成效率明显提高。
The implementation of automatic test generation and fault diagnosis is also discussed.
还讨论了测试码自动生成和故障诊断的具体实现方法。
After the test generation process is complete, the test suite will open in the test Editor view.
当测试生成过程完成之后，测试集将在TestEditor视图中打开。
Based on the stuck-at fault analysis, state test generation for synchronous circuits is presented.
通过分析时序电路固定故障的状态变换，提出基于状态隐含变换的测试方法。
The test generation algorithm for non-robust path delay fault in combinational circuits is studied.
研究了组合电路中非鲁棒性路径时滞故障的测试生成算法。
A constraint extraction method and a constraint path delay test generation algorithm are developed.
研究并实现了约束提取及约束下的非强健通路时延测试产生算法。
Two main aspects in VLSI testing, fault simulation and test generation, are researched in this dissertation.
本文对VLSI测试中的两个主要问题—故障模拟和测试产生进行了深入的分析和研究。
An interoperability test generation method based on MSC (message sequence charts) test purposes was presented.
提出了一种基于MSC(消息序列图)测试目的的互操作性测试生成方法。
A kind of model data and the preprocessing method for the logic circuit test generation system (TGS) are presented.
讨论了逻辑电路测试生成系统(简称TGS)中使用的一种模型数据及预处理方法。
Using Binary Decision Diagrams, this paper proposes a test generation method for functional level digital circuits.
本文利用二叉判定图提出了对功能级数字电路的一种测试产生方法。
This paper describes state transition fault and collapsing of test generation basis of the character of fixed fault.
详细分析了固定故障所反映出的状态变换特征，提出状态变换故障模型以及相对应的测试生成压缩方法；
The parallel test generation technology is an important method to resolve the difficult problem of test on massive circuits.
并行测试技术是解决当今大规模电路测试难题的一个重要手段。
Experimental results show that by using the techniques, the number of faults to be tested for test generation decreases greatly.
实验结果表明，这些精简故障的方法较大幅度的精简了需要进行测试产生的目标故障数。
We propose a new approach of functional testing for microprocessor systems and discuss the hardware associated and test generation.
针对微处理器系统测试问题，提出了一种全新的功能测试方法。
This paper presents an interoperability test generation method based on the formal model, Communicating Multiport Finite State Machines.
文章提出了一种基于通信多端口有限状态机模型的协议互操作性测试生成方法。
In addition, its built-in data correlation filters detect variable data, as well as preparing tests for data-driven load test generation.
另外，它的嵌入式数据相关性过滤器能够检查可变数据，并根据数据驱动加载测试需求进行测试。
Low coverage indicates a process problem, which might require test generation technique to be improved, or training to be imparted to the tester.
低的覆盖率表明方法有问题，可能是测试生成技术需要改进，也可能需要给测试人员提供培训。
This dissertation focuses on automatic test generation (ATPG) algorithms for very large-scale integrated circuits at register-transfer-level (RTL).
本文主要是对大规模、超大规模集成电路寄存器传输级（RTL）的自动测试产生算法进行研究。
This paper presents a high speed test generation method specifically for upper large scale combination circuit (ULSCC) and full scan designed circuit.
针对特大规模组合电路和全扫描设计电路提出了一种高速测试生成方法。
This paper propose a functional fault for delay faults in combinational circuits and describe a functional test generation procedure based on this model.
提出一种用于测试组合电路中延迟故障的新功能故障模型，讨论该模型的功能测试生成。
The result indicates that the technology manipulates easily and is effective, the fault coverage reaches 90%, it is a feasible test generation technology.
仿真结果表明，该方法操作简单、有效，故障覆盖率达到了90%，是一种很可行的存储器板测试生成方法。
Besides fault collapsing, this paper also proposes some techniques, such as code collapsing, change of the ending rules to optimizing the test generation algorithm.
结合故障精简，本文通过编码压缩、变化终止规则等方法进一步优化了全速电流测试方法的测试产生算法。
The technique of automatic testing is mainly for test carrying out, result catching and analyzing, result validating and reporting, and is lack for test generation.
然而，现有的自动测试技术大多是针对测试执行、结果捕获与分析、结果验证和报告等方面的，针对测试用例自动生成的还很少。
The results show that the circuit model and the test generation algorithm are not only effective for generating test sequence but also can help for the testability analyse.
试验数据显示，该模型和测试生成算法不仅对生成测试序列是有效的，而且对于电路描述的可测性分析也有一定的帮助。
In addition, the detailed analysis of some frequently used memory test algorithms and brief analysis of some test generation algorithms for VLSI are also included in this paper.
另外本文还比较详细的分析比较了常用的存储器测试算法，简要分析了VLSI测试生成算法。
The description of the abstract test suit using TTCN-3 language only completed part of the test generation, the implementation of test need for an environment, namely testing system.
使用TTCN - 3语言描述抽象测试套只是完成了测试生成部分，测试套的执行需要一个运行环境，即测试系统。
This paper presents an efficient sequential circuit automatic test generation algorithm. The algorithm is based on self - adapting algorithm and USES a seventeen - valued logic model.
本文提出了一种高效的时序电路测试生成算法，该算法是建立在自适应算法的基础上，并使用了十七值逻辑模型。
This paper presents an efficient sequential circuit automatic test generation algorithm. The algorithm is based on self - adapting algorithm and USES a seventeen - valued logic model.
本文提出了一种高效的时序电路测试生成算法，该算法是建立在自适应算法的基础上，并使用了十七值逻辑模型。
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