A method of designing asynchronous sequential circuits is presented.
本文提出异步时序电路的设计方法。
A new method for designing synchronous sequential circuits (SSC's) is described.
介绍了一种设计同步时序逻辑电路的新方法。
How to implement the initialization for synchronous sequential circuits is a important issue.
如何实现同步时序电路的初始化是时序电路测试中的关键问题。
This paper presents a new approach to the automatic generation of initialization for synchronous sequential circuits.
本文针对时序电路的初始化提出一种新的实现方法。
Testing generation of un test faults is a major factor influencing the efficiency of sequential circuits testing generation.
对不可测故障进行测试产生是影响时序电路测试产生效率的一个重要因素。
In the paper authors present a new approach of speeding up power estimation of CMOS sequential circuits by circuit simplication.
文章提出了一种采用电路化简加速功耗估计的方法。
An improved algorithm based on register mapping is proposed to increase the speed of equivalence checking for sequential circuits.
为了提高时序电路的等价性验证速度，提出一种改进的基于寄存器匹配的验证算法。
Presented and implemented in this paper is a fanout source based fault parallelism fault simulator for synchronous sequential circuits.
从工程应用的角度出发，同步时序电路故障模拟采用单测试码故障并行的模拟结果更能反映实际情况。
In design of pulsed asynchronous sequential circuits, it will solve for equations of clock and equations of state, on a symbolic Karnaugh map.
在异步时序电路设计中，它将时钟方程和状态方程的求解归在统一的符号卡诺图上进行。
It can translate the bit level description of the specification of combinational circuits and sequential circuits into word level polynomials.
它能把组合电路和时序电路的位级描述的设计规范表示成字级多项式。
This paper presents a transition function method which can be extended to solve the synthesis problems of multiple variable sequential circuits.
本文提出迁移函数法。用此方法可以解决多变量时序电路综合问题。
The logic functions of MSI counter 74161 was analysed. It could be taken as a universal sequential module to realize any synchronous sequential circuits.
分析了MSI计数器74161的逻辑功能，它作为通用的时序部件可以实现任意同步时序电路。
Some design examples show that the design of synchronous sequential circuits based on next state equations of flip-flops is of great advantage and practical significance.
通过设计实例表明，基于触发器次态方程设计同步时序电路具有一定的优点和实用意义。
The paper also discusses the design principle of super-high-speed digital circuits and some examples of combinational and sequential circuits using linear AND-OR gate are given.
本文还讨论了应用线性“与或”门设计超高速数字电路的准则以及有关的组合和时序电路设计实例。
It is rather difficult to analyze and make use of asynchronous sequential circuits, so the application of asynchronous sequential circuits is much narrower than synchronous ones.
对异步时序电路的分析和使用是一个比较困难的问题，所以，异步时序电路的实际应用范围远不如同步时序电路。
Therefore, it not only greatly reduces the design procedure of sequential circuits, but can also meet the need of contemporary design on its systematization, clarity and reliability.
这不仅大大简化了时序电路的设计过程，而且能满足现代设计关于系统性、清晰性和可靠性的要求。
Base on the existing synchronous sequential circuits fault simulator-HOPE, the test vector generation method of sequential circuits based on ant algorithm is systematically researched firstly.
本文在同步时序电路故障模拟器—HOPE的基础上，率先对基于蚂蚁算法的时序电路测试矢量生成方法作了系统的开拓性研究。
According to different sensitive transitions of flip-flops used in sequential circuits, design and analysis methods for asynchronous sequential circuits are proposed by using the combinatorial clock.
本文根据电路中采用的触发器的不同敏感沿，提出采用组合时钟的异步时序电路的设计和分析方法。
In pattern generation for sequential circuits at RTL, simulation-based methods avoid the large search space used in time-frame expansion methods, but the quality of patterns cant be guaranteed often.
在时序电路的RTL激励生成中，基于模拟的方法避免了帧扩展法庞大的搜索空间，但采用该方法常存在向量过多，质量不高等问题。
The methods have useful reference value to using correctly flip-flops and designing sequential logic circuits.
这些方法对于正确使用触发器和设计时序逻辑电路有重要应用参考价值。
This paper is a discussion on some teaching methods of the simplification for Karnaugh map, the analysis of sequential circuit and the teaching of integrated circuits.
对数字电路中卡诺图化简、时序电路分析和集成电路教学等三个问题的教学方法进行一定的分析和探讨。
In this paper, DT flip - flop excitation table is developed, the design method of sequential logic circuits using DT flip - flop is presented, and the design example using the method is given.
导出了DT触发器的激励表，提出了应用DT触发器的时序逻辑电路的设计方法，并给出了设计实例。
When it connects to ARM, driving circuits (sequential logical circuits) is necessary because CMOS star sensor doesn't belong to I2C bus circuits.
CMOS敏感器不是I2C总线电路，因此同arm连接必须有驱动电路(时序逻辑电路)。
In the past twenty years, people have studied extensively and proposed several effective verification methods for sequential behaviors of digital circuits, such as simulation method and formal method.
在过去的二十几年中，人们对于数字电路顺序行为的验证进行了深入的研究并提出了许多行之有效的验证方法，例如，模拟的方法和形式化的方法等。
Pipeline circuits that have high working frequency and a large number of sequential elements, are easily affected by soft error.
流水线电路具有工作频率高、时序单元数量多的特点，易受软错误影响。
Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
应用推荐