This paper constructs the function simulation platform for buffer manager and the whole system, and validates the design on the platform after the RTL design.
在完成该单元的RTL级设计的基础上，进一步构建了该单元及整个系统的功能仿真平台，在该平台上验证了设计的正确性。
The work of this dissertation is to complete the RTL design and verification of CLB-PVCI bus bridge after studying and analyzing the CLB bus protocol and PVCI protocol.
本论文工作就是在研究和分析CLB总线协议和PVCI协议的基础上，完成CLB - PVCI总线桥的RTL设计和验证。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
The company's capabilities cover the entire IC design spectrum from RTL design, though verification, emulation and DFT to physical implementation, and include power analysis and yield management.
公司设计能力涵盖从RTL设计、验证、仿真和DFT到物理实现的整个IC设计体系，并且包括功耗分析和良率管理。
Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain.
由于寄存器传输级(rtl)行为描述可以精确地确定数字系统的操作，所以寄存器传输级综合成为当前EDA行业的主流设计方法。
As the behavior of digital system can be fully described by the register transfer level (RTL) behavior descriptor, so RTL synthesis has become the mainstream design method in EDA domain.
寄存器传输级(rtl)综合实现从rtl行为描述到门级结构描述的转换，是目前EDA设计行业的主流设计方法。
The IC design method base on RTL has been widely used.
集成电路设计在寄存器传输级的设计方法已经非常成熟。
Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
The design includes system level design, RTL level design and logic synthesis.
设计工作包括系统级设计、RTL级设计、逻辑综合。
The design of MCS-51 Microcontroller is followed the Top-Down design way, including system partition coding (VHDL) RTL simulation synthesis, gate level simulation ect.
对MCS—51单片机进行正向设计，包括系统划分、编写代码、RTL级仿真与综合、门级仿真等。
The three key modules are all presented as RTL level design and module functional simulation. The deinterlacing system's FPGA design is in the last chapter.
本文对于这三个去隔行系统的关键模块都给出了RTL级设计和模块的功能仿真，并在最后一章中给出了去隔行系统的FPGA设计。
The main task is translating the behavioral description of a digital system into the design of RTL(Register Transfer Level).
高层次综合也叫行为级综合，其基本任务是完成数字系统行为描述到寄存器传输级（RTL）描述的转换。
Lead ASIC frond-end design team to complete Synthesis, STA, Equivelant Check, Post Layout Simulation, DFT, ATE, Power Control. Make sure RTL code is ok for chip implement.
负责带领整个团队实施芯片的综合、静态时序分析、逻辑一致性分析、后仿真、DFT、ATE、功耗控制。从芯片实现的角度对模块的RTL代码和芯片的RTL代码进行把关。
By comparing the trace of simulator with that of the processor RTL model, design faults can be quickly and accurately located.
模拟器的运行结果与处理器RTL模型的结果进行对比，大大方便了对RTL模型的验证和查错。
By comparing the trace of simulator with that of the processor RTL model, design faults can be quickly and accurately located.
模拟器的运行结果与处理器RTL模型的结果进行对比，大大方便了对RTL模型的验证和查错。
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