This paper studies the crosstalk fault and its methods of test pattern generation in high-speed interconnect circuits.
本论文针对高速互连电路串扰型故障及测试生成方法进行研究。
The paper proposes controlling input values tracing algorithm and test derivation algorithm based on test pattern generation using satisfiability.
以组合电路的满足性测试生成算法为基础，提出了控制输入跟踪算法和测试衍生算法。
There is a bright future for the pattern generation technology in decorating pattern design, such as furniture clothing design, decorating fresco design, hotel decoration pattern design, etc.
这种图案生成技术在装饰图案设计如家居布艺设计、装饰壁画设计、宾馆装饰品图案设计等领域有着广阔的前景。
In order to reduce the storage requirements for the test patterns, a vertical and horizontal test data compression BIST scheme based on the test pattern generation of twisted-ring counter is proposed.
为了减少测试向量的存储需求，提出一种基于扭环计数器作为测试向量产生器的横向和竖向测试数据压缩的BIST方案。
In pattern generation for sequential circuits at RTL, simulation-based methods avoid the large search space used in time-frame expansion methods, but the quality of patterns cant be guaranteed often.
在时序电路的RTL激励生成中，基于模拟的方法避免了帧扩展法庞大的搜索空间，但采用该方法常存在向量过多，质量不高等问题。
In pattern generation for sequential circuits at RTL, simulation-based methods avoid the large search space used in time-frame expansion methods, but the quality of patterns cant be guaranteed often.
在时序电路的RTL激励生成中，基于模拟的方法避免了帧扩展法庞大的搜索空间，但采用该方法常存在向量过多，质量不高等问题。
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