Thus, it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate.

因此研究系统总线协议及其实现技术对于隐藏访存延迟和提高访存速度具有重要意义。

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Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.

片外存储系统的访存延迟主要由DRAM延迟决定，带宽则是由内存总线的数据传输率所决定。

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As clock speed and the number of processors increase, it becomes increasingly difficult to reduce the memory latency required to use this additional processing power.

随着处理器时钟速度的提高和处理器数量的增加，使用这种额外处理能力所需的内存滞后时间越来越难以减少。

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As clock speed and the number of processors increase, it becomes increasingly difficult to reduce the memory latency required to use this additional processing power.

随着处理器时钟速度的提高和处理器数量的增加，使用这种额外处理能力所需的内存滞后时间越来越难以减少。

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