The processor is connected to physical memory by the memory bus.
处理器通过内存总线连接到物理内存。
NUMA reduces the contention for a system's Shared memory bus by having more memory buses and fewer processors on each bus.
通过使用更多的内存总线，并令每条总线上处理器更少，NUMA减少了系统共享内存总线的冲突。
Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.
片外存储系统的访存延迟主要由DRAM延迟决定，带宽则是由内存总线的数据传输率所决定。
NUMA alleviates these bottlenecks by limiting the number of CPUs on any one memory bus and connecting the various nodes by means of a high speed interconnection.
NUMA通过限制任何一条内存总线上的CPU数量并依靠高速互连来连接各个节点，从而缓解了这些瓶颈状况。
Physical Shared memory bus, message translating LAN and copy Shared memory network are the main interconnecting technology using in distributed real-time simulation.
分布式仿真系统可采用的联接方式主要有物理共享内存总线、消息传递网络和复制共享内存网络三种。
Physical Shared memory bus, message translating LAN and copy Shared memory network are the main interconnecting technology using in distributed real-time simulation.
分布式仿真系统可采用的联接方式主要有物理共享内存总线、消息传递网络和复制共享内存网络三种。
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