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memory bus
[ˈmeməri bʌs] [ˈmeməri bʌs]

  • [计] 存储器总线

专业释义英英释义

  • 存储总线 - 引用次数:4

    参考来源 - 基于存储总线的可重构硬件加速部件研究与设计
    内存总线 - 引用次数:3

    参考来源 - 机群通信系统互连接入技术研究
    储栖线
    存储器总线
    记忆总线
    记忆体汇流排
  • 存储栖线

·2,447,543篇论文数据,部分数据来源于NoteExpress

Memory bus

  • abstract: The memory bus is the computer bus which connects the main memory to the memory controller in computer systems. Originally, general-purpose buses like VMEbus and the S-100 bus were used, but to reduce latency, modern memory buses are designed to connect directly to DRAM chips, and thus are designed by chip standards bodies such as JEDEC.

以上来源于: WordNet

双语例句权威例句

  • The processor is connected to physical memory by the memory bus.

    处理器通过内存总线连接物理内存。

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  • NUMA reduces the contention for a system's Shared memory bus by having more memory buses and fewer processors on each bus.

    通过使用更多内存总线总线处理器更少NUMA减少系统共享内存总线的冲突。

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  • Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.

    片外存储系统的访延迟主要DRAM延迟决定带宽内存总线数据传输率所决定。

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