In this paper, DT flip - flop excitation table is developed, the design method of sequential logic circuits using DT flip - flop is presented, and the design example using the method is given.
导出了DT触发器的激励表，提出了应用DT触发器的时序逻辑电路的设计方法，并给出了设计实例。
The design of ternary D type flip-flop and T type flip - flop has been improved. Thetwo flip-flops have perfect preset functions.
对三值维持阻塞D型和T型触发器的设计进行了改进，使它们具有完善的预置功能。
To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.
从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。
Taking the latch composed of two inverters as basic storage unit, this paper proposes a novel CMOS JK flip-flop based on the design at switch level.
该文以双反相器闩锁电路为基本存贮单元，采用开关级设计方法设计出一种新型的CMOSJK触发器。
The parallel loading of the flip-flop can be synchronous (i. e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.
触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟)，这取决于移位寄存器的设计。
Original conditions: Use D flip-flop (74 LS 74), " and" gate (74 LS 08), " or" gate (74 LS 32), non-gate (74 LS 04), three binary mod 5 counter design.
原始条件：使用D触发器（ 74LS 74 ）、“与”门 （ 74 LS08 ）、“或”门（ 74 LS32 ）、非门 （ 74 LS04 ），设计三位二进制模5计数器。
Original conditions: Use D flip-flop (74 LS 74), " and" gate (74 LS 08), " or" gate (74 LS 32), non-gate (74 LS 04), three binary mod 5 counter design.
原始条件：使用D触发器（ 74LS 74 ）、“与”门 （ 74 LS08 ）、“或”门（ 74 LS32 ）、非门 （ 74 LS04 ），设计三位二进制模5计数器。
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