flip-flop design 触发器设计
In this paper, DT flip - flop excitation table is developed, the design method of sequential logic circuits using DT flip - flop is presented, and the design example using the method is given.
导出了DT触发器的激励表，提出了应用DT触发器的时序逻辑电路的设计方法，并给出了设计实例。
The design of ternary D type flip-flop and T type flip - flop has been improved. Thetwo flip-flops have perfect preset functions.
对三值维持阻塞D型和T型触发器的设计进行了改进，使它们具有完善的预置功能。
To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.
从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。
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