A new type of DPLL is introduced in this paper.
介绍了一种新型的数字锁相环。
Renaming for CNF formulas may help to improve DPLL algorithm.
研究CNF公式的改名有助于改进DPLL算法。
How to raise the phase lock speed of embedded DPLL is researched.
对如何提高嵌入式全数字锁相环的锁定速度进行了研究。
The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.
数字锁相环路（DPLL）是数字相干解调技术的核心。
In this paper, the basic principle of this DPLL and the concept of the dynamic probability transformation characteristic are proposed.
本文简述了它的工作原理，并在前人分析的基础上提出了滤波器动态概率变换特性的概念。
The experimental results indicate the circuit is credible and the program runs well. The DPLL based on DSP is competent for ultra-audio frequency-tracking.
实验结果证明基于DSP的DPLL完全可以胜任超音频的频率跟踪，系统硬件电路可靠，程序运行良好。
Unlike previous researches, the nonlinear analysis on the effects of delay-difference module employed in the delay phase-locked loop (DPLL)is particularly presented.
与以往研究不同，针对延迟锁相线性化环路的延迟差分环节，着重分析了其非线性特性对环路性能的影响。
Traditional Lag-Lead synchronous DPLL shortcomings slow. In order to solve this problem, proposed a method for FPGA-based realization method of fast bit synchronization.
针对传统超前-滞后型数字锁相环实现同步速度较慢的缺点，提出了一种基于步进和量化调整的数字锁相法的快速位同步方法。
Additionally, a hardware DPLL is constructed and tested to provide a comparison to the results obtained from the Markov chain model. It is found that the theoretical predictions are in...
另外，针对一个硬件DPLL进行了测试，与马尔可夫链模型获得的结果进行比较，发现理论预测与实验能很好地吻合。
Based on nonlinear loop models, quantitative analysis on noise performance and capture procedure of the DPLL is performed. The simulation results are in good accordance with the experimental data.
利用非线性环路模型对环路的噪声性能和捕捉过程进行了定量分析，仿真结果与实测数据吻合得较好。
Based on nonlinear loop models, quantitative analysis on noise performance and capture procedure of the DPLL is performed. The simulation results are in good accordance with the experimental data.
利用非线性环路模型对环路的噪声性能和捕捉过程进行了定量分析，仿真结果与实测数据吻合得较好。
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