The system is of double clock design structure which makes the odd verifying circuit structure simple and easily effected.
系统采用双时钟设计结构，使得奇校验电路结构简单、易实现。
Just like Intel's super high clock rates don't translate into proportionately more performance, doubling of cache size certainly doesn't double the performance of a microprocessor.
就像英特尔的超高时钟频率不能在提升了，双核内存也不能让微处理器的功能增大一倍。
Alternatively, most in-room televisions also double up as an alarm clock.
另外，大部分的房间电视，也应该设有闹铃功能。
The trick is to use a clocked DLL, which not only minimizes clock skews, but also offers a double-frequency output clock.
关键是为了使用时钟DLL，它不只是最小化时钟脉冲相位差，还提供双倍输出的时钟频率。
It is clear that Fermi's real performance advantage would be Double Precision performance - had it hit the right clock speeds.
显然，费米的实际性能上的优势将是双精度性能-如果它击中的时钟速度。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.
从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。
Alarm clock, colour TV, connecting room, hair dryer, mini - bar in room, shampoo, tooth brush, one king - sized bed or two double beds in all rooms.
闹钟，彩色电视，相连房间，干发器，室内小型酒吧，洗发露，牙刷，所有客房均备有一张特大睡床或两张双人床。
This paper introduces a user terminal equipment for the double-satellite positioning system. The terminal, named continuous navigation passive positioning system, is based on Rubidium atomic clock.
介绍了一种基于铷钟的双星系统用户终端机——连续导航无源双星定位系统。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
模拟结果表明所设计的触发器具有正确的逻辑功能，跟传统的时钟低摆幅双边沿触发器相比，降低近17%的功耗。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
模拟结果表明所设计的触发器具有正确的逻辑功能，跟传统的时钟低摆幅双边沿触发器相比，降低近17%的功耗。
应用推荐