MAI管理设备控制器内的所有状态寄存器，并且通过8位并行数据线与设备端mcu进行数据交换。
MAI, which manages all the control status registers, exchange data with MCU through 8-bit data bus.
输出数经74164输出的8位并行数据送至8段LED，实现测量数据的显示，实现可视的计数功能。
The output number delivers to 8 section of LED after 74164 outputs8 bit parallel data, the realization survey data demonstration, realizes visibly count...
应用汇编语言编写了二次引导程序，采用16位并行异步存储器加载方式，实现计量单元上电自动运行。
Assemble language was used to write second boot loader, and 16-bit parallel asynchronous memory Loading mode was adopted to achieve automatic run after energization.
通过实际运行证明该16位并行输入输出接口通讯电路达到了设计指标，圆满完成了配合整个控制系统的任务。
The experimental results prove that this 16 Bit parallel data communication interface attains the performance index and accomplishes the task of c...
主要介绍一种利用FLASH存储器实现TMS320 VC 5402系列DSP的存储器扩展，并结合实例对8位并行加载的全过程做了详细的介绍。
Mainly introduces TMS320VC5402 series DSP storage spreading realized by applying FLASH storage and the complete process of 8 bits parallel loading combined with living examples in detail.
通过研究EBCOT编码原理和通道并行算法的编码过程，提出了双上下文窗口位并行的EBCOT系数位建模方法，详细说明了使用该算法的系数位建模系统的硬件结构。
After the detailed analysis of EBCOT algorithm and pass-parallel coding technique, a dual context window bit-parallel coding method and its architecture for hardware implementation are proposed.
每个操作都是并行地针对多个数据元素进行，这些数据分别存储在一些128位的寄存器中。
Every operation works on multiple data elements in parallel, stored in 128-bit registers.
然而，为了让iMic具有适度的性能，我们在本系列文章中的目标是处理两个并行的(立体声)44.1kHz的16位数据流，这就意味着要实现22.05 kHz的音频带宽。
However, in line with the modest capabilities of the iMic, our target for this series is to work with two parallel (stereo) 44.1khz 16-bit data streams, implying an audio bandwidth of 22.05khz.
本文简要地介绍量子计算的一些基本概念：量子纠缠、量子位、量子寄存器、量子并行计算和量子纠错。
In this paper we briefly introduce some basic concepts of quantum computing which include quantum entanglement, quantum bit, quantum register, quantum parallel computing and quantum error correction.
同时这种并行处理方法也适合于其它位宽的CRC电路，为高速数据的可靠传输提供了可靠保障。
This parallel processing method is fit for other bit-wide CRC, and provides reliability for high-speed data transferring as well.
为实现快速编码，该文提出一种位平面、过程双重并行编码方法，可以大幅度提高编码速度。
For fast encoding, the bit-plane and pass dual-parallel approach is presented in this paper, which reduces the encoding time significantly.
基于粘贴模型的巨大并行性，给出了一类禁位排列问题的粘贴DNA算法，分别使用扩展的分离操作和扩展的多级分离操作实现了该算法。
A sticker DNA algorithm is proposed based on the vast parallelism of sticker model, and be carried out it by extended separate and extended multi-separate respectively.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
压缩比达到了1.9以上，与其它超光谱图像压缩算法相当。位平面变换算法具有很好的并行性。
The compression ratio of algorithm is more than 1.9. The compression algorithm based on bit plane transform can be realized by parallel computing model.
研究了现有的位平面编码VLSI结构，设计了一种条带列与编码通道全并行的VLSI结构，解决了内部存储资源占用率高的问题。
According to the research on the existing VLSI architecture of the bit-plane coding, a new VLSI architecture is proposed in which stripe-column and coding are both implemented in parallel.
在FPGA读取视频信息后，先用位面分层技术把串行视频信息转换为并行数据再送到视频电缆上。
After video information read by FPGA, serial video information is transformed into parallel format by Bit-Plane Separation technology first, and then sent to video cable.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
给出了实现1 6位数据并行通讯的接口原理图。
It presents the principle chart of the interface for 16 bits parallel data communication.
当保密位被激活后，除芯片擦除外的所有并行编程命令都被忽略(这样就不能对器件执行读操作)。
When the Security Bit is activated all parallel PROGRAMMING commands except for Chip-Erase are ignored (thus the DEVICE cannot be read).
将主从式并行遗传算法应用于托卡马克等离子体平衡位形优化问题，这是一个工程中实际存在的大搜索空间优化问题。
The optimization of tokamak plasma equilibrium shape, which is considered as a problem with large search space, is solved using master-slave PGAs.
以较低造价实现多32位CPU并行高速运行，远优于单cpu，具有很高的可靠性。
Based on several low - cost high - performance 32 - bit CPUs working together, the system is more reliable than those based on just one CPU.
采用与位平面数目相同的上下文形成模块实现位平面并行处理。
Bit planes are coded by context format (CF) modules in parallel.
但如果你是位滑板手，那就是快乐与痛苦并行。
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
变字长解码模块的核心是基于桶形移位器的并行解码结构，使用该结构的解码速度比一次一位的串行结构更快。
The serial structured decoder can decode one bit per cycle. Because the structure of UVLC(Universal Veriable Length Code) is fixed, "first one detector"is designed to decode UVLC.
输出的时钟信号普适于多通道多相 位时钟应用，尤其适用于并行交替型模数转换器。
An output clock signal is universally suitable for the application of the multi-channel multi-phase clock, and is particularly suitable for a parallel alternate type analog-to-digital converter.
输出的时钟信号普适于多通道多相 位时钟应用，尤其适用于并行交替型模数转换器。
An output clock signal is universally suitable for the application of the multi-channel multi-phase clock, and is particularly suitable for a parallel alternate type analog-to-digital converter.
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