The parallel perturbation technique is well-suited to mixed-mode VLSI implementation.
该并行扰动技术非常适合于用混模vlsi实现。
The VLSI implementation of neural networks is an effective approach to facilitate its use.
神经网络的超大规模集成电路(VLSI)实现是发挥其优势的有效途径。
In this paper, a VLSI implementation method of design-for-testability for DCT is presented.
本文提出了一种离散余弦变换电路VLSI实现的可测试性设计。
The storage of neural network weight is an important problem of VLSI implementation to be solved.
神经网络的权值存储是集成电路实现技术中涵待解决的重要问题。
Based on the full use of parallel architecture, an efficient solution for VLSI implementation is described.
在采用并行结构的基础上，给出了一种高效的VLSI实现方案。
In this paper, we present a bit plane-parallel architecture for zero tree coding which is suitable for VLSI implementation.
提出了比特平面并行处理的零树编码结构。
The simulation result shows that it can function correctly with fast recognition speed; therefore, it is suitable for VLSI implementation of neural network.
模拟结果表明其功能正确，具有较高的识别速度，适于神经网络的VLSI实现。
A new lattice polynomial perceptron (LPP) model is derived, which is very suitable for VLSI implementation. Computer simulations have been carried out and the experimental results are given.
导出了便于VLSI实现的多项式感知器的格型实现算法，进行了计算机模拟，并给出了相应的数值结果。
A new lattice polynomial perceptron (LPP) model is derived, which is very suitable for VLSI implementation. Computer simulations have been carried out and the experimental results are given.
导出了便于VLSI实现的多项式感知器的格型实现算法，进行了计算机模拟，并给出了相应的数值结果。
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