A via hole is formed in the substrate within the spirally patterned conductor layer, the via hole being formed by through silicon via (TSV).
介层洞形成于螺旋图案化导体层内部的基材中，该介层洞通过硅通孔技术制成。
The methods of 3d interconnection can be classified into the wire bonding, flip chip, through silicon via (TSV) and film wire technology, whose advantages and disadvantages are analyzed.
将实现3d互连的方法分为引线键合、倒装芯片、硅通孔、薄膜导线等，并对它们的优缺点进行了分析。
This article will review today's challenges, along with such future trends as integration and through-silicon via(TSV) technologies.
概述当今的挑战，以及这些集成和硅通孔技术的未来趋势。
Semiconductor analysis with ANSYS tools often incorporates nonlinear behaviors, including package warpage, solder joint creep, fracture in through-silicon-via designs, fatigue and delimitation.
利用ANSYS工具，可以分析半导体的非线性特性，其中包括封装变形、焊接点蠕变以及过孔设计中的断裂、疲劳和层间开裂。
Semiconductor analysis with ANSYS tools often incorporates nonlinear behaviors, including package warpage, solder joint creep, fracture in through-silicon-via designs, fatigue and delimitation.
利用ANSYS工具，可以分析半导体的非线性特性，其中包括封装变形、焊接点蠕变以及过孔设计中的断裂、疲劳和层间开裂。
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