• The measurement accuracy was sub-micron grade.

    测量精度为亚微米量级。

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  • Finally, composite sub-micron particles exhibit superparamagnetic property.

    最后,混合亚微粒显示有超顺磁特性。

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  • TEM images indicate that the composite sub-micron particles are nearly spherical.

    TEM影像表明混合物亚微粒接近球状。

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  • Thin films are widely used in MEMS with different thicknesses from micron, sub-micron to nanometer scale.

    MEMS中大量使用薄膜材料,厚度可达微米、亚微米直至纳米量级。

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  • With the advent of the era of deep sub-micron IC, the feature size on the IC chip is shrunk to nanometers.

    伴随着深亚微米集成电路时代的来临,芯片的特征尺寸已经缩小到纳米尺度。

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  • A synthesis system of equation-based deep sub-micron cell-level CMOS analog circuit is presented in the paper.

    介绍了一个基于公式的深亚微米CMOS模拟单元电路综合系统。

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  • Finally, the initial structure of light guide plate with sub-micron gratings is given and the error is analyzed.

    给出亚微米光栅型光导板的初始结构,并进行了误差分析。

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  • We present a novel method, used to build the I-V characteristic equations of the MOSTs in the deep sub-micron circuits.

    提供了一种新的方法,用于建立深亚微米电路中MOST的伏安特性方程。

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  • Well-dispersed sub-micron ceria was prepared successfully through direct thermal decomposition of hydrated cerium acetate.

    以水合醋酸铈为前驱体,经直接煅烧制备了亚微米级超细氧化铈,且粒子分布窄,分散性好。

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  • Current design trends have shown that crosstalk issues in deep sub-micron can cause severe design validation and test problems.

    超深亚微米工艺下,串扰的出现会导致在电路设计验证、测试阶段出现严重的问题。

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  • Dust collector is designed to separate superfine particle or even sub-micron dust from process gas with micropore fiber material.

    过滤除尘器是利用微孔超细纤维滤布分离气体和微细粉尘,乃至亚微米尘埃的主要设备。

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  • A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.

    介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。

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  • The present invention further relates to a deep sub-micron MOS integrated circuit die comprising a thick-oxide transistor-based preamplifier.

    本发明还涉及一种深亚微米mos集成电路管芯,包括基于厚氧化物晶体管的前置放大器。

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  • We demonstrate a quasi-periodic structure exhibiting multiple photonic band gaps (PBGs) based on sub-micron-period poled lithium niobate (LN).

    我们在本文中提出了基于亚微米准周期极化铌酸锂实现多波长光子禁带的结构。

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  • The wide-range flexure hinge-based parallel manipulator system can provide sub-micron scale precision over the cubic centimeter scale workspace.

    基于大行程柔性铰链的并联机器人系统可以在立方厘米级的工作空间内提供亚微米级的运动精度。

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  • A new approach is proposed for the measurement of micron grade and sub-micron grade single particle size by the use of acoustic wave entrainment.

    文中提出了一种新的利用声波夹带测量微米级和亚微米级单颗粒粒径的方法。

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  • The thermal resistance of DSOI devices is very close to that of bulk devices and DSOI devices can keep this advantage into deep sub-micron realm.

    DSOI器件的衬底热阻和体硅器件非常接近,并且在进入到深亚微米领域以后能够继续保持这一优势。

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  • This paper presents the design and realization of a new type of video format conversion IC with LSI, deep sub-micron and analog-digital compatibility.

    介绍了一种新型的超大规模、深亚微米、模数兼容的视频格式转换芯片的设计与实现。

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  • As the semiconductor manufacturing process technology into the deep sub-micron or even nanometer, power consumption is becoming increasingly prominent.

    随着集成电路工艺制程进入超深亚微米甚至纳米级,集成电路的功耗问题显得日益突出。

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  • At present, the semiconductor devices used in the manufacturing process of etching technology, in the lab has produced sub-micron mechanical components.

    目前,利用半导体器件制造过程中的蚀刻技术,在实验室中已制造出亚微米级的机械元件。

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  • A new method for layout design based on region constraints was presented to resolve the timing closure problem of physical design in deep sub-micron technology.

    针对深亚微米工艺下版图设计中存在的时序收敛问题,提出了一种区域约束的版图设计方法。

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  • Composition and surface properties of obtained composite sub-micron particles have been studied in comparison with those of ferrite-free PLGA sub-micron particles.

    将由此而来的混合亚微粒的组分和表面性质与不含铁氧体的PLGA亚微粒进行了对比研究。

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  • It is a process that produces polymer fibers with diameter in the sub-micron range under the action of an external electric field imposed on a polymer solution or melt.

    它是一种借助于静电场作用对聚合物溶液或熔体进行纺丝的过程,它所形成的纤维直径为亚微米级。

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  • Based on simulation, the characteristics and mechanisms of failure on a deep sub-micron grounded-gate NMOS (GGNMOS) are studied under TLP (transmission line pulse) stress.

    对TLP(传输线脉冲)应力下深亚微米ggnmos器件的特性和失效机理进行了仿真研究。

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  • It has been demonstrated that compared to simulator-based method, manufacturable deep sub-micron CMOS analog circuits can be synthesized using this system in a short run time.

    大量的实验结果表明:与基于模拟器的方法相比,采用该系统可以快速综合出可制造的深亚微米cmos模拟单元电路。

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  • By use of this technique, we fabricated scaffold-like micro-well structures with sub-micron resolution and high aspect ratio by both raster scanning and pinpoint scanning methods.

    与其它微加工技术比较,使用此方法除可制作复杂的三维微结构外,同时它又具有免用光罩、制作步骤简单、真正三维的立体结构及高解析度之优点。

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  • The accurate measurements of local micro-stress and strain in ultra deep sub-micron semiconductor structures usually resort to complicated microstructure analysis, measurement methods.

    超深亚微米半导体结构中的局域微应力、应变的精确测量通常必须借助复杂的微结构分析、测量手段。

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  • In this paper, design technologies of sub-micron CMOS gate array, such as building library, testability, clock design, power-ground design, architecture optimizing, margin design, are presented.

    本文主要论述亚微米cmos门阵列的设计技术,包括建库技术,可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等,最后给出了应用实例。

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  • Sub-micron accuracy of displacement detection is obtained by adopting edge fitting technology and path matching technology.

    该方法采用边界拟合和“路径匹配”技术,使位移量的检测精度达到了亚微米级。

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  • This paper presented the various technologies in RF design and explored the feasibility and difficulties of deep sub micron CMOS RF design. And problems associated are also discussed.

    本文介绍了当今RF设计的主流工艺,并分别对基于硅的深亚微米cmos工艺在RF设计中的可行性和困难进行了研究,评述了其中存在的问题。

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