Traditional Lag-Lead synchronous DPLL shortcomings slow. In order to solve this problem, proposed a method for FPGA-based realization method of fast bit synchronization.
针对传统超前-滞后型数字锁相环实现同步速度较慢的缺点，提出了一种基于步进和量化调整的数字锁相法的快速位同步方法。
Traditional Lag-Lead synchronous DPLL shortcomings slow. In order to solve this problem, proposed a method for FPGA-based realization method of fast bit synchronization.
针对传统超前-滞后型数字锁相环实现同步速度较慢的缺点，提出了一种基于步进和量化调整的数字锁相法的快速位同步方法。
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