There has to be some gap of clock cycles between the unblocking of signals and the next instruction carried by the process, and any occurrence of a signal in this window of time is lost.
从消除信号阻塞到进程执行下一个指令之间，必然会有时钟周期间隙，任何在此时间窗口发生的信号都会丢掉。
C1E tries to provide more power savings than the traditional C1 state (which only halts the clock signal) by also lowering the voltage and frequency.
同样通过降低电压和频率，C1E尝试比传统C1状态(只会停止时钟信号)提供更大的电能节省。
Clock signal and clock skew become more and more important in the circuit performance.
时钟信号和时钟偏差对电路性能的影响也越来越明显。
The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs.
转换过程和数据采集过程通过CS和串行时钟信号进行控制，从而为器件与微处理器或DSP轻松接口创造了条件。
According to the logic chip design feature, the chip work's time signal can be divided into 4 kinds: clock signal, input signal, combination output signal and register output signal.
按照逻辑芯片设计特点，将芯片工作时的信号分为4种：时钟信号、输入信号、组合输出信号和寄存器输出信号。
The high frequency clock allows for a greater sampling rate, which results in higher accuracy and faster signal processing capability .
高频时钟可支持更高的取样率，从而达到更高的精确度和更快的信号处理能力。
The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。
The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal.
你的微型计算机执行程序的速度将与你的时钟信号的速度成线性关系。
We know that the hardware circuit design clock signal is the most important one of the signals.
我们知道，在硬件电路设计中时钟信号是最重要的信号之一。
The device always generates the clock signal.
时钟信号总是由设备端生成的。
These functions are realized by the circuits of power, clock, memory, ultrasonic pulse signal occurs and handle, temperature gathered and serial communication in system.
这些功能的实现是通过系统中电控部分的电源、时钟、存储、超声波脉冲信号发生、处理、温度采集、串行通信电路实现的。
Its function is to provide a latching switch action upon sensing an input threshold voltage, with reset accomplished by an external clock signal.
它的功能是当感应到输入电压界限时提供一个锁存开关，通过外部时钟信号完成复位。
Until almost 12 o 'clock, and dads just outside with firecrackers into a long, waiting for the ignition signal.
待到快到12点，爸爸们就在屋外用爆竹摆成一条长龙，等待点火信号。
A binary tree routing topology is designed for propagating the system clock and trigger signal and the accurate timing and synchronization between sensors are provided by CPLD.
设计了二进制树型拓扑结构传播统一的系统时钟和触发信号，采用CPLD提供传感器间的精确时序和同步。
In order to accomplish the data process and conversion, the clock generation circuit, 100% modulation signal and 10% signal demodulation circuit are designed.
为了完成数据的处理和交换，分别设计了时钟产生电路、100%调制信号和10%调制信号的解调电路。
The author introduces the design of digital display clock, the time signal received by GPS satellite receiver corrects time automatically after receiving and processing by single chip computer.
介绍一种利用GPS卫星接收机接收的时间信号，经单片机接收处理后进行自动校时的数显时钟的设计。
A method for subdividing the grating pulse signal by means of using computer clock pulse is presented in this paper.
本文介绍了一种利用计算机时钟脉冲细分光栅脉冲信号相位的方法——改进型时钟脉冲细分技术。
In clock routing, clock signal and clock skew become more and more important for impact of the circuit performance.
在时钟布线中，时钟信号和时钟偏差对电路性能的影响越来越明显。
The latest three-phase clock signal control method was used to control the working state of charge pump.
电路采用了预启动和衬底电位选择结构，并利用三相时钟信号方式控制电荷泵的工作状态。
The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
该系统采用了片同步技术实现了采样后高速数字信号的可靠锁存，采用高精度的时钟管理芯片和设计合理的时钟路径对时钟抖动做了严格控制。
The synthesized test system for underwater weapon system adopts a modularized structure with signal generator, A/D converter, D/A converter, real-time clock, printer and LCD screen.
水下武器系统综合检测系统采用模块化设计思想，由信号发生器模块、A/D模块、D/A模块、实时时钟模块、液晶及打印机模块等组成。
Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream.
位同步时钟信号的提取是通信系统中的关键部分，应用数字锁相环可以准确地从输入码流中提取出位同步信号。
One of the most critical points in optical PPM radio communication lies on the recovery of slot clock and frame synchronization signal.
P PM无线光通信的关键问题之一在于时隙时钟与帧同步信号的恢复。
The data acquisition system consists of the signal conditioning circuit, DSK interfacing circuit, RS-485 communication interfacing circuit, system clock circuit, the power circuit, and so on.
数据采集系统包括信号调理电路、DSK接口电路、RS- 485通信接口电路、系统时钟电路及电源电路等。
These persistent registers are powered by a battery and receive a timing clock signal from a crystal oscillator.
这些持续不断的寄存器由电池供电，并接收来自晶体振荡器计时的时钟信号。
The paper presents a square wave modulation scheme based on TDMA signal system to resolve the problem. Also it can avoid the high speed system clock.
该文提出了一种基于TDMA信号体制下的方波调制方案，该方案既解决了远近效应，又避免了在较高的中频上采用过高的系统时钟。
The control circuit of the Kilowatt-hour meter consists mainly of the circuit of signal detection, real-time clock and control of output, and it also consists of 68hc705c8 single chip computer.
该电度表的控制电路主要由信号检测、实时时钟、输出控制电路及68hc 705c8单片机组成。
The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.
在突发式的接收模块中，逻辑电平的恢复和时钟数据的恢复是其关键的问题。
The interface circuit also can produce synchronous, vanished and ensconced, digital clock signal and realize remote control, displaying on screen.
同时产生同步、消隐、数据时钟等信号以及实现遥控、屏幕显示的控制功能。
The interface circuit also can produce synchronous, vanished and ensconced, digital clock signal and realize remote control, displaying on screen.
同时产生同步、消隐、数据时钟等信号以及实现遥控、屏幕显示的控制功能。
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