The design includes system level design, RTL level design and logic synthesis.
设计工作包括系统级设计、RTL级设计、逻辑综合。
The three key modules are all presented as RTL level design and module functional simulation. The deinterlacing system's FPGA design is in the last chapter.
本文对于这三个去隔行系统的关键模块都给出了RTL级设计和模块的功能仿真，并在最后一章中给出了去隔行系统的FPGA设计。
Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain.
由于寄存器传输级(rtl)行为描述可以精确地确定数字系统的操作，所以寄存器传输级综合成为当前EDA行业的主流设计方法。
As the behavior of digital system can be fully described by the register transfer level (RTL) behavior descriptor, so RTL synthesis has become the mainstream design method in EDA domain.
寄存器传输级(rtl)综合实现从rtl行为描述到门级结构描述的转换，是目前EDA设计行业的主流设计方法。
The Register Transfer Level (RTL) behavioral descriptions are widely used in IC designs.
寄存器传输级（RTL）描述是目前应用最广泛的电路设计描述形式。
The main task is translating the behavioral description of a digital system into the design of RTL(Register Transfer Level).
高层次综合也叫行为级综合，其基本任务是完成数字系统行为描述到寄存器传输级（RTL）描述的转换。
Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level (RTL) is a promising solution.
验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。
Transaction level modeling hides unnecessary details. The communication at transaction level is method calls in comparison with signals and pins at RTL.
事务级建模在RTL级之上，忽略了不必要的细节，把模块之间的通信方式从管脚和信号方式抽象为函数调用。
RTL and FPGA are used to validate high-level models while software tools are used for tasks such as workload analysis.
RTL和FPGA主要用于验证高级语言模型，各种辅助工具可以用于工作负载的分析和优化。
The design of MCS-51 Microcontroller is followed the Top-Down design way, including system partition coding (VHDL) RTL simulation synthesis, gate level simulation ect.
对MCS—51单片机进行正向设计，包括系统划分、编写代码、RTL级仿真与综合、门级仿真等。
This paper proposes and implements a novel verification and RTL-Level bug locating method for microprocessors.
本文提出并实现了一种新的基于指令分解的微处理器验证与RTL级错误定位方法。
This dissertation focuses on automatic test generation (ATPG) algorithms for very large-scale integrated circuits at register-transfer-level (RTL).
本文主要是对大规模、超大规模集成电路寄存器传输级（RTL）的自动测试产生算法进行研究。
RTL(register transfer level) functional verification system for package assembly function in IPOA application is illustrated in this paper.
介绍一种对IPOA应用中的组包功能进行RTL功能验证的系统。
Still others would say that ESL refers to anything that's at a higher level of abstraction than register transfer level (RTL) representations.
还有一些人会说esl是优于寄存器传输级(rtl)的更高的抽象层次。
Still others would say that ESL refers to anything that's at a higher level of abstraction than register transfer level (RTL) representations.
还有一些人会说esl是优于寄存器传输级(rtl)的更高的抽象层次。
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