Most RISC processors are big-endian.
大多数RISC处理器都是big - endian。
Support for the newly released HP-UX Version 11.23 release on PA-RISC.
对新发布的HP - UXVersion 11.23releaseon PA - RISC的支持。
It consisted of over 100 instructions and was known as a complex RISC system.
它包含超过100种指令，被称为复杂的RISC系统。
Its six RISC processors can morph into different programming modes for reconfigurable data flow.
它的6个RISC处理器能提供不同的编程模式，重新配置数据流。
During the early 1990's, there were five different RISC architectures that were actively competing with one another.
在90年代早期，有五种不同的RISC体系结构，竞争非常激烈。
The structure of RISC is very simple.
RISC具有结构简单、指令简单的特点。
RISC design is register file operation oriented.
RISC设计是面向寄存器堆操作的。
Introduce to a 64-bit RISC microprocessor design.
文章介绍了一种64位RISC微处理器的结构设计。
ARM embedded processor is a high performance, low - power RISC chips.
ARM嵌入式处理器是一种高性能、低功耗的RISC芯片。
The model is based on 32 bits RISC, and other modules can be configured.
该模型基于32位RISC构建，并可配置其它硬件模块。
The emphasis in CPU design shifted to raw performance, and RISC became the new philosophy.
CPU设计的重点转到了提高性能上，RISC成了新的(设计)思想。
In RISC OS SWIs are used to access Operating System routines or modules produced by a 3rd party.
在RISCOS中使用SWI来访问操作系统例程或第三方生产的模块。
The development of instruction level power model is discussed to our self-made LS-RISC microprocessor.
针对笔者自主研制的LS -RISC微处理器，讨论了其指令级功耗模型的开发。
The MIPS architecture embodies the fundamental design principles of all contemporary RISC architectures.
MIPS架构体现了当代所有的RISC架构的基本设计原则。
RISC chips use a rather small number of relatively simple, fixed-length instructions, always 32 bits long.
RISC芯片采用数量较少、较为简单的固定长度指令，总是32位长。
This paper describes a synthetic RISC architecture CPU design and implementation in detail for teaching experiment.
详细介绍了用VHDL语言设计可逻辑综合的教学实验用CPU的过程。
In fact, most modern CISC processors actually translate their instructions to an internalized RISC format for efficiency.
实际上，现代CISC处理器将自己的指令转换成了内部使用的risc格式，以实现更高的效率。
But last month the company received an initial round of funding from Caixa capital Risc, a Spanish venture capital company.
但上个月公司收到了首轮来自西班牙一家风险投资公司CaixaCapital Risc的基金。
This paper describes an approach to instruction system-based on behavioral functional level test of MB86901 SPARC RISC chip.
本文提出了一种基于指令系统的MB86901SPARCRISC芯片的行为功能级测试方法。
However, due to the limitation of embedded chips, it is impossible to complete the whole process of software development on RISC chips.
但由于嵌入式芯片性能的局限性，无法在RISC芯片上完成整个软件开发过程。
RISC avoided this problem by keeping every instruction at the same length, making it easier for instructions to be pipelined in parallel.
RISC通过保证每一个指令的长度相等的方法避免了这个问题，使指令在并行结构中更容易被流水线操作。
The first chip actually had several chips on one single motherboard, but was refined to one RISC chip with more than 1 million transistors.
第一个芯片实际上在一个主板上有几个芯片，但是优化为一个包含超过一百万个晶体管的RISC 芯片。
This paper introduces the design of RISC microprocessor with pipelining based on FPGA, which is included the design of key modules and pipelining.
文章介绍了基于FPGA的流水线RISC微处理器的设计，包括关键模块设计和流水线设计。
Samsung's S3C4510B 16/32-bit RISC microcontroller is based on ARM core and applied broadly because of its cost-effective, high-performance feature.
S3C4510B是三星公司生产的基于ARM核的16/32位RISC微处理器，因其很高的性价比而得到广泛的应用。
Network processors overcome the limitations of these two approaches by combining the programmability of RISC processors with the performance of ASICs.
网络处理器通过把RISC处理器的可编程性与ASIC的性能结合起来，克服这两种方法的局限性。
Remember that the main advance of RISC was to integrate all these ideas into a single architecture model, coupled with a coherent top-down methodology.
应该记住，RISC的主要优势在于将所有这些概念集成于一个单一的结构模型中，并配以连贯的自上而下的方法。
The YH-ITM intelligent tool machine is an RISC-based general-purpose intelligent computer system which supports several AI languages and the traditional c.
智能工具机YH - ITM是一个基于RISC、支持多种人工智能语言和传统C语言的通用智能计算机系统。
The design problem of an embedded RISC architecture in parallel processing of algorithm level, instruction level and process level is discussed in this paper.
本文将从算法级并行处理、指令级并行处理与进程级并行处理等三个方面讨论嵌入式RISC体系结构的设计问题。
The design problem of an embedded RISC architecture in parallel processing of algorithm level, instruction level and process level is discussed in this paper.
本文将从算法级并行处理、指令级并行处理与进程级并行处理等三个方面讨论嵌入式RISC体系结构的设计问题。
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