Most RISC processors are big-endian.
大多数RISC处理器都是big - endian。
For RISC processer, clock-gating can reduce power by 18.8%.
对于risc微处理器，门控时钟技术可以降低功耗18.8%。
RISC: RISC is the acronym for "reduced instruction set computing".
精简处理：英文是“减少指令组的电脑处理”的字首字。
ARM embedded processor is a high performance, low - power RISC chips.
ARM嵌入式处理器是一种高性能、低功耗的RISC芯片。
Support for the newly released HP-UX Version 11.23 release on PA-RISC.
对新发布的HP - UXVersion 11.23releaseon PA - RISC的支持。
The model is based on 32 bits RISC, and other modules can be configured.
该模型基于32位RISC构建，并可配置其它硬件模块。
The emphasis in CPU design shifted to raw performance, and RISC became the new philosophy.
CPU设计的重点转到了提高性能上，RISC成了新的(设计)思想。
Its six RISC processors can morph into different programming modes for reconfigurable data flow.
它的6个RISC处理器能提供不同的编程模式，重新配置数据流。
The development of instruction level power model is discussed to our self-made LS-RISC microprocessor.
针对笔者自主研制的LS -RISC微处理器，讨论了其指令级功耗模型的开发。
The MIPS architecture embodies the fundamental design principles of all contemporary RISC architectures.
MIPS架构体现了当代所有的RISC架构的基本设计原则。
RISC chips use a rather small number of relatively simple, fixed-length instructions, always 32 bits long.
RISC芯片采用数量较少、较为简单的固定长度指令，总是32位长。
During the early 1990's, there were five different RISC architectures that were actively competing with one another.
在90年代早期，有五种不同的RISC体系结构，竞争非常激烈。
It was originally based on System v, release 3, and it ran exclusively on their RISC - PA-RISC HP 9000 platform.
它最初基于SystemVrelease3，只能在RISC- PA - RISC HP 9000平台上运行。
RISC microprocessor is developed by using modular design method and VHDL language based on FPGA and EDA technology.
基于FPGA和电子设计自动化技术。采用模块化设计的方法和VHDL语言，设计一个基于FPGA的RISC微处理器。
Also on the processor front RISC systems themselves saw a 32.7% increase in revenue and a 15.3% increase in units shipped.
另外，在前端处理器RISC系统上，出现了32.7%的收入增长和15.3%的安装数量增长。
ARM RISC performs call process, protocol process, net management and user interface, these are normal process function.
ARMRISC完成呼叫处理、通信协议的转换、网络的管理以及用户界面的支持，这些则属于一般性的处理功能。
In fact, most modern CISC processors actually translate their instructions to an internalized RISC format for efficiency.
实际上，现代CISC处理器将自己的指令转换成了内部使用的risc格式，以实现更高的效率。
But last month the company received an initial round of funding from Caixa capital Risc, a Spanish venture capital company.
但上个月公司收到了首轮来自西班牙一家风险投资公司CaixaCapital Risc的基金。
Thirdly, RISC design can support all function of exchanging, storing, editing, searching, and modifying the business cards.
采用简单指令集的设计，能在系统内完成全部的交换、存储，编辑、查询、修改名片等操作。
The Power architecture stands for Power Optimization with Enhanced Risc and is the processor used by IBM midrange servers today.
POWER体系结构表示带有增强的Risc功能的“功率优化”，并且是当今ibm中型服务器所使用的处理器。
This paper describes an approach to instruction system-based on behavioral functional level test of MB86901 SPARC RISC chip.
本文提出了一种基于指令系统的MB86901SPARCRISC芯片的行为功能级测试方法。
Coversely, the highly programmable RISC-based solutions have almost unlimited flexibility, but they sacrifice so much speed.
而高可编程性RISC基解决方案具有很大灵活性，但它牺牲了太多的速度。
Aim at the problem, ARM (Advanced RISC Machines) CMOS chip was adopted for remote control of automobile electron door locks.
针对这一问题，本文描述的汽车电子控制门锁的遥控仪器采用ARM(先进的精简指令微处理器)芯片。
The first chip actually had several chips on one single motherboard, but was refined to one RISC chip with more than 1 million transistors.
第一个芯片实际上在一个主板上有几个芯片，但是优化为一个包含超过一百万个晶体管的RISC 芯片。
However, due to the limitation of embedded chips, it is impossible to complete the whole process of software development on RISC chips.
但由于嵌入式芯片性能的局限性，无法在RISC芯片上完成整个软件开发过程。
RISC avoided this problem by keeping every instruction at the same length, making it easier for instructions to be pipelined in parallel.
RISC通过保证每一个指令的长度相等的方法避免了这个问题，使指令在并行结构中更容易被流水线操作。
This paper proposes a new method of RISC architecture design, in which most of the instructions have been implemented by single machine cycle.
提出了大多数指令在单周期内实现是RISC结构设计的新方法。
The major tenet of RISC states that much of the static runtime complexity can and should be handle prior to runtime by an optimizing compiler.
RISC的主要原则表明许多固定运行时间的复杂指令可以并且应该由优化编译器先于运行时间进行处理。
Network processors overcome the limitations of these two approaches by combining the programmability of RISC processors with the performance of ASICs.
网络处理器通过把RISC处理器的可编程性与ASIC的性能结合起来，克服这两种方法的局限性。
Network processors overcome the limitations of these two approaches by combining the programmability of RISC processors with the performance of ASICs.
网络处理器通过把RISC处理器的可编程性与ASIC的性能结合起来，克服这两种方法的局限性。
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