The power-optimized processor system bus remains powered down until it senses incoming data form the chipset, allowing to the processor to consume less power.
电源优化的处理器系统总线始终处于断电状态，直到感知来自芯片组的数据才通电，从而减少处理器的耗电量。
As an external interface of the processor, system bus component affects the efficiency of memory system directly.
作为处理器的片外接口，系统总线部件直接影响着存储系统的效能。
We study the split transaction pipelining technology in detail, and apply it to the implementation of system bus component in X processor.
本文详细研究了这种分离事务流水执行技术并应用该技术实现了X处理器系统总线部件。
A host controller transfers data over a bus communication system, under the control of a processor, in individual transactions.
一种主机控制器在处理器的控制下经由总线通信系统在单独事务中传送数据。
The opening structure of the STD BUS managed by a Z80 processor helps to build up a flexible and expansible data acquisition system.
由Z80微处理器管理的STD总线开放式结构具有灵活地扩充、方便地获取数据等特点。
This system with the control core of 80c552 single chip processor adopts bus isolation technique, realizing the time-sharing processing of high-speed data collecting and data processing.
该系统以80c552单片机为控制核心，采用总线隔离技术，实现高速数据采集与数据处理分时进行。
A bus-structure flight control system using DSP as processor is designed, which aims at the demands of power, cost and integration from small Unmanned Aerial Vehicle(UAV).
针对小型无人机控制系统对功耗、成本、可集成性等的较高要求，设计了一种基于DSP芯片TMS320F2812的总线式飞行控制系统。
A bus-structure flight control system using DSP as processor is designed, which aims at the demands of power, cost and integration from small Unmanned Aerial Vehicle(UAV).
针对小型无人机控制系统对功耗、成本、可集成性等的较高要求，设计了一种基于DSP芯片TMS320F2812的总线式飞行控制系统。
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