...据称可能会是两个wolfdale芯片的集合,每个单芯片集成最大容量12MB的二级缓存,采用1066MHz的处理器总线(processor system bus)标准,预计在2007年Q4开始出货。
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The power-optimized processor system bus remains powered down until it senses incoming data form the chipset, allowing to the processor to consume less power.
电源优化的处理器系统总线始终处于断电状态,直到感知来自芯片组的数据才通电,从而减少处理器的耗电量。
As an external interface of the processor, system bus component affects the efficiency of memory system directly.
作为处理器的片外接口,系统总线部件直接影响着存储系统的效能。
We study the split transaction pipelining technology in detail, and apply it to the implementation of system bus component in X processor.
本文详细研究了这种分离事务流水执行技术并应用该技术实现了X处理器系统总线部件。
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