This thesis describes the system design of a high-resolution pipelined ADC.
论述 了高速高精度流水线结构模数转换器的设计。
The Pipelined ADC architecture has the characteristics of high sampling rate as well as high resolution.
流水线结构ADC具有能同时实现高采样速率和高分辨率的特点。
Due to its high precision and high sampling rate, research and design on pipelined ADC are widely attention to.
由于具有高精度和高采样速率等优点，流水线结构ADC的研究和设计引起了广泛关注。
To reduce the power dissipation and chip size of digital calibration circuits of pipelined analog-to-digital converter (ADC), a new statistics-based background calibration technique is presented.
为了降低流水线模数转换器中数字校准电路的规模和功耗，提出了一种新的基于信号统计规律的后台数字校准技术。
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic.
这款双通道adc内核采用多级、差分流水线架构，并集成了输出纠错逻辑。
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic.
这款双通道adc内核采用多级、差分流水线架构，并集成了输出纠错逻辑。
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