...样保持; 倍乘数模转换器; 流水线ADC; 有效位数 [gap=920]Key words: sample and hold; multiplying DAC (MDAC) ; pipelined ADC; effective number of bits ...
基于60个网页-相关网页
运算放大器电路被广泛应用于采样保持电路和乘法型数模转换器(Multiplying-DAC, MDAC)中,是流水线式模数转换器(Pipelined ADC)的核心模块之一,它的性能直接影响了流水线式模数转换器的各项关键性能指标。
基于40个网页-相关网页
A 10-bit 110 MS/s pipelined ADC for video front-end is designed and silicon certificated.
最后,设计了一个用于视频前端的10位110MS/s流水线ADC,并完成了流片和测试。
参考来源 - 标准数字CMOS工艺下高速流水线模数转换器的研究与设计·2,447,543篇论文数据，部分数据来源于NoteExpress
This thesis describes the system design of a high-resolution pipelined ADC.
论述 了高速高精度流水线结构模数转换器的设计。
The Pipelined ADC architecture has the characteristics of high sampling rate as well as high resolution.
流水线结构ADC具有能同时实现高采样速率和高分辨率的特点。
Due to its high precision and high sampling rate, research and design on pipelined ADC are widely attention to.
由于具有高精度和高采样速率等优点，流水线结构ADC的研究和设计引起了广泛关注。
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