The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
说明了对偶基比特并行乘法器在硬件规模上的优越性。
A new high regular structure of partial parallel multiplier for irreducible trinomial generated finite field is proposed.
提出了一类新的具有高度规则性的部分并行三项式有限域乘法器架构。
DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.
数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
The presentation of the finite field elements in WDB is studied. And based on the computing method for the optimum WDB, the design for the bit parallel multiplier of finite field is presented.
研究了有限域元素在弱对偶基（WDB）下的表示，基于弱对偶基下的最优弱对偶基的计算方法，给出了有限域比特并行乘法器的设计；
An algorithm for the parallel realization of multiplier is presented in this paper by combining redundant Residue Number System (RRNS) with redundant binary represent.
将剩余数系统算术和冗余二进制表示算术相结合，提出了一种并行实现乘法器的算法，这种算法不仅具有溢出检测功能，而且具有容错能力。
An algorithm for the parallel realization of multiplier is presented in this paper by combining redundant Residue Number System (RRNS) with redundant binary represent.
将剩余数系统算术和冗余二进制表示算术相结合，提出了一种并行实现乘法器的算法，这种算法不仅具有溢出检测功能，而且具有容错能力。
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