... voltage multiplier 倍压器,电压倍增器... parallel multiplier 并联乘法器 electrical multiplier 电动倍加器 ...
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bit parallel multiplier 位并行乘法器
serial-parallel multiplier 串并乘法器
partial parallel multiplier 部分并行乘法器
parallel-plate channel multiplier 平行板通道式倍增器
parallel processing multiplier 平行处理乘法器 ; [计] 并行处理乘法器
serial-in parallel-out multiplier 串入并出乘法器
straight parallel channel electron multiplier 直平行通道式电子倍增器
parallel l multiplier 并行乘法器
Parallel Integer Multiplier 并行整数乘法器
The implementation and simulation of a 6-bit parallel multiplier is presented to demonstrate that the new reconfigurable array can reduce the time complexity of fault-tolerance and improve the utilization rate of the redundancy resources.
以6×6并行乘法器为例,验证了新型可重构阵列能够降低容错时间复杂度并提高冗余资源利用率。
参考来源 - 可重构硬件内建自测试与容错机制研究·2,447,543篇论文数据，部分数据来源于NoteExpress
The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
说明了对偶基比特并行乘法器在硬件规模上的优越性。
A new high regular structure of partial parallel multiplier for irreducible trinomial generated finite field is proposed.
提出了一类新的具有高度规则性的部分并行三项式有限域乘法器架构。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
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