The implementation and simulation of a 6-bit parallel multiplier is presented to demonstrate that the new reconfigurable array can reduce the time complexity of fault-tolerance and improve the utilization rate of the redundancy resources.
以6×6并行乘法器为例,验证了新型可重构阵列能够降低容错时间复杂度并提高冗余资源利用率。
参考来源 - 可重构硬件内建自测试与容错机制研究·2,447,543篇论文数据，部分数据来源于NoteExpress
The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
说明了对偶基比特并行乘法器在硬件规模上的优越性。
A new high regular structure of partial parallel multiplier for irreducible trinomial generated finite field is proposed.
提出了一类新的具有高度规则性的部分并行三项式有限域乘法器架构。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
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