The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
说明了对偶基比特并行乘法器在硬件规模上的优越性。
Actually most companies base their model on a 60% margin, which would lead to a 2.6x multiplier, but I'm applying a bit of a discount to capture that initial Maker altruism.
事实上，大部分公司都是60%是提价，这会产生2.6倍的乘积，但是我考虑了一点优惠，可以获得第一批客户。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
The presentation of the finite field elements in WDB is studied. And based on the computing method for the optimum WDB, the design for the bit parallel multiplier of finite field is presented.
研究了有限域元素在弱对偶基（WDB）下的表示，基于弱对偶基下的最优弱对偶基的计算方法，给出了有限域比特并行乘法器的设计；
Based on the characteristic of multi-path frequency selective channel, the algorithm combines rapid table lookup and Lagrange-multiplier method to iteratively search the optimal bit allocation scheme.
算法根据多径信道选择性衰落的特性，结合查表法和拉格朗日乘子的混合迭代搜索法，最优地分配各个子载波的传输比特数。
CONCLUSION We designed a 16 bit high performance signed multiplier.
我们设计了一个16位高性能带符号乘法器。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
应用推荐