Given these trends, it was expected that memory latency would become an overwhelming bottleneck in computer performance.
鉴于这些趋势，预计内存延迟将成为压倒性的计算机性能的瓶颈。
Thus, it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate.
因此研究系统总线协议及其实现技术对于隐藏访存延迟和提高访存速度具有重要意义。
Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.
片外存储系统的访存延迟主要由DRAM延迟决定，带宽则是由内存总线的数据传输率所决定。
As clock speed and the number of processors increase, it becomes increasingly difficult to reduce the memory latency required to use this additional processing power.
随着处理器时钟速度的提高和处理器数量的增加，使用这种额外处理能力所需的内存滞后时间越来越难以减少。
Memory and CPU based access can provide much lower latency and greater throughput than disk and network based access.
相比基于磁盘和网络的访问，基于内存和CPU的访问能提供更低的延迟和更高的吞吐量。
This increases the latency of the task's memory access until its data is in the cache of the new CPU.
这就增加了任务的内存访问延迟，这些时间用来将其数据移入新cpu的内存中。
Due to the latency difference between main memory and on-chip memory cache, POWER7 was designed with three levels of on-chip cache (see Figure 1).
由于主内存和芯片级内存缓存之间的延迟差别，POWER 7设计了三种级别的芯片级缓存机制(见图1)。
The tightly-coupled nature of the CMP allows very short physical distances between processors and memory and, therefore, minimal memory access latency and higher performance.
CMP紧密耦合的本质使处理器与内存之间的物理距离很短，因此可提供最小的内存访问延迟和更高的性能。
For example, each processor has its own memory but also access to Shared memory with a different access latency.
例如，每个处理器拥有自己的内存，访问共享内存时具有不同的访问延迟。
Review your data on a week-to-week basis and monitor stats that reflect CPU utilization, disk usage, mail delivery latency (if you are running mail), memory utilization, and network utilization.
每周定期查看数据，并监控反映cpu利用率、磁盘使用、邮件发送延迟(如果运行邮件的话)、内存利用率和网络利用率的统计数据。
Experience shows that memory databases provide superior performance and low latency.
经验表明，内存数据库可以提供出色的性能和很低的延迟。
To to minimize access latency, and thus improve performance, it's best to have your data in the closest memory.
为了尽可能减少访问延时并由此提高性能，最好把数据放在最近的内存中。
"Throughput, latency, and memory usage have been further optimized to improve performance for your applications." Security enhancements.
吞吐量，延迟与内存使用被进一步优化，从而改进应用程序的性能。
Each processor has equal access to the Shared memory (the same access latency to the memory space).
每个处理器可同等地访问共享内存(具有相同的内存空间访问延迟)。
The new native user interface also uses much less memory than the previous version, and resolves some performance and latency problems.
新的原生用户界面也比原来的版本减少了内存占用，解决了一些性能和潜在的问题。
The percentage of used memory depends on the application, the size of request and response messages, and the volume and latency of requests.
已使用内存的百分比取决于应用程序、请求和响应消息的大小，以及请求的数量和延时。
All modern CPUs must utilize local memory cache to minimize latency of fetching instructions and data from memory.
所有现代的CPU必须使用本地存储的缓存，将获取指令和数据的延迟降到最低。
One relies upon an in memory queue as we prefer very low latency between when a bid is placed and when it appears in My eBay.
一个是依靠内存中的队列，因为我们希望尽量缩短从出价到在显示在“我的eBay”页面上之间的响应时间。
METHODS: Pharmacological model of amnesia in mice was induced by scopolamine. Memory result was evaluated by the step-through latency in the passive-avoidance task.
方法：用东莨菪碱造成小鼠记忆损伤的模型，应用被动避暗试验测定潜伏期以评价记忆成绩。
Controller is calculated for the standard the memory DDR2 SDRAM and allows the possibility of programming latency.
控制器的计算标准内存的DDR2SDRAM，并允许的可能性，方案延迟。
Software pipelining has been combined with several memory optimization technologies for higher performance by hiding memory access latency.
为了减轻存储系统影响，软件流水结合了一些存储优化技术，通过隐藏存储延迟来提高性能。
If your cloud system supports it, keep this table in memory (" custom Settings ") versus on-disk for lower latency.
如果你的云系统支持此功能，把这个列表放入内存(“自定义设置”)来减少磁盘读取的等待时间。
Results: The model rat had obvious learning and memory disorder, and had significantly longer escape latency in the orientation navigation experiment as compared with that of false operation group;
结果：模型大鼠表现出明显的学习记忆障碍，在定位航行实验中，与假手术组相比，逃避潜伏期显著延长；
This Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoders using traditional trace-back methods.
与采用传统回溯法的译码器相比，该译码器具有较低的译码时延、有效的存储空间管理和较低的硬件复杂度。
The normal and control rats showed less and less the escape latency and mistakes than model rats, indicating learning, memory and spacial function.
和模型组相比，正常和假手术组随时间延长游完全程的时间以及错误次数逐渐减少，学习、记忆和空间辨别能力较强。
A method, system and computer program product for eliminating the latency in searching for contiguous memory space by an IO DMA request of a device driver.
一种方法、系统和计算机程序产品，用于消除在按照设备驱动程序的IODMA请求来搜索邻接存储器空间时产生的等待。
A method, system and computer program product for eliminating the latency in searching for contiguous memory space by an IO DMA request of a device driver.
一种方法、系统和计算机程序产品，用于消除在按照设备驱动程序的IODMA请求来搜索邻接存储器空间时产生的等待。
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