The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
Level restoration pass-transistor logic is proposed for low speed cell while dynamic transmission gate logic for high speed cell.
低速单元采用带有电平恢复的传输管逻辑实现，高速单元采用动态传输门逻辑实现。
The pre-functional cell of standard buffered FET logic (BFL) adopted by the gate array possesses nine logic functions, two different kinds of driving capabilities, and the level control ability.
此门阵列采用的BFL预功能级标准逻辑单元，具有九种组合逻辑功能及两种不同选择的驱动能力，并具有输出电平调节功能。
Using gate level modeling might not be a good idea for any level of logic design.
使用门级建模对于任何逻辑设计都不是一个好的设计。
Using gate level modeling might not be a good idea for any level of logic design.
使用门级建模对于任何逻辑设计都不是一个好的设计。
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