... 逻辑闸 logic gate 逻辑闸级 logic gate level 逻辑产生语言 logic generating language，LOGEL ...
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gate level logic simulation [计] 门级逻辑模拟
low level logic gate 低电平逻辑门电路
gate-level logic simulation 门级逻辑模拟
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
Level restoration pass-transistor logic is proposed for low speed cell while dynamic transmission gate logic for high speed cell.
低速单元采用带有电平恢复的传输管逻辑实现，高速单元采用动态传输门逻辑实现。
The pre-functional cell of standard buffered FET logic (BFL) adopted by the gate array possesses nine logic functions, two different kinds of driving capabilities, and the level control ability.
此门阵列采用的BFL预功能级标准逻辑单元，具有九种组合逻辑功能及两种不同选择的驱动能力，并具有输出电平调节功能。
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