In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate.
此外，缓冲层可以减少晶体管之间的设备和硅衬底平行的传导问题。
We try to obtain the common-base current gain a of the parasitic PNP transistor from the eloping profile of the collector region including the effect of buried-layer.
本文从包括埋层影响的集区杂质分布出发，求出了寄生PNP晶体管的共基极电流放大系数。
In one embodiment, a thin film transistor comprises a layer of the organic semiconductor material.
在一个实施方案中，薄膜晶体管包含有机半导体材料层。
A semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics and reliability is provided in the present invention.
本发明的目的之一在于使用氧化物半导体层提供具备其电特性及可靠性优异的薄膜晶体管的半导体装置。
The present invention provides a thin film transistor in which aluminum atoms are unlikely to be diffused to an oxide semiconductor layer.
本发明提供了一种其中铝原子不可能扩散到氧化物半导体层的薄膜晶体管。
According to the present invention, formation of lattice defect in an oxide semiconductor layer and entering of moisture can be prevented, improving reliability of the thin film transistor.
本发明能够抑制氧化物半导体层中晶格缺陷的形成并抑制湿气的进入，从而提高薄膜晶体管的可靠性。
A hetero-structure field effect transistor (HFET), may include a first layer (3) made from a first semiconductor material and a second layer (4) made from a second semiconductor material.
一种异质结构场效应晶体管(HFET)，可以包括由第一半导体材料制成的第一层(3)和由第二半导体材料制成的第二层(4)。
A membrane transistor, including a semiconductor layer, an inner-island shaped structure composed of the upper semiconductor layer and the lower semiconductor layer.
本发明主要是提供一种薄膜晶体管，其包括有一半导体层、一下重掺杂半导体层与一上重掺杂半导体层构成的内岛状结构。
A transistor may be formed with a first polysilicon layer covered by a dielectric.
晶体管可以形成为具有被电介质覆盖的第一多晶硅层。
Each transistor may be formed from a gate insulating layer formed on a semiconductor.
每个晶体管可以由形成在半导体上的栅极绝缘层形成。
In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.
此外，缓冲层地址和缓解晶格薄膜之间的不匹配而相对形成晶体管和硅衬底上。
In an embodiment, the transistor can include a semiconductor layer having a primary surface and a conductive structure.
在一实施方式中，晶体管可包括具有主表面的半导体层和传导结构。
The invention provides a memory cell transistor having multi-layer tunnel insulator and memory device.
本发明提供一种具有多层隧道绝缘体的存储器单元晶体管及存储器器件。
A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided.
提供了一种包括薄膜晶体管的半导体器件，该薄膜晶体管具有氧化物半导体层和优秀的电特性。
The invention discloses a lower grid electrode-based film transistor which comprises a grid electrode, a grid electrode insulating layer, and a micro-crystallization silicon layer;
本发明公开了一种下栅极式薄膜晶体管，包含栅极、栅极绝缘层以及微结 晶硅层。
The invention discloses a lower grid electrode-based film transistor which comprises a grid electrode, a grid electrode insulating layer, and a micro-crystallization silicon layer;
本发明公开了一种下栅极式薄膜晶体管，包含栅极、栅极绝缘层以及微结 晶硅层。
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